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| Octal, 14-Bit, 50 MSPS Serial LVDS 1.8 V A/D Converter AD9252 FEATURES 8 ADCs integrated into 1 package 93.5 mW ADC power per channel at 50 MSPS SNR = 73 dB (to Nyquist) Excellent linearity DNL = 0.4 LSB (typical) INL = 1.5 LSB (typical) Serial LVDS (ANSI-644, default) Low power reduced signal option, IEEE 1596.3 similar Data and frame clock outputs 325 MHz, full power analog bandwidth 2 V p-p input voltage range 1.8 V supply operation Serial port control Full-chip and individual-channel power-down modes Flexible bit orientation Built-in and custom digital test pattern generation Programmable clock and data alignment Programmable output resolution Standby mode FUNCTIONAL BLOCK DIAGRAM AVDD PDWN DRVDD DRGND AD9252 VIN+A VIN-A VIN+B VIN-B VIN+C VIN-C VIN+D VIN-D VIN+E VIN-E VIN+F VIN-F VIN+G VIN-G VIN+H VIN-H VREF SENSE 0.5V REFT REFB REF SELECT SERIAL PORT INTERFACE ADC 14 SERIAL LVDS 14 ADC 14 ADC 14 ADC 14 ADC 14 ADC 14 ADC 14 ADC SERIAL LVDS SERIAL LVDS SERIAL LVDS SERIAL LVDS SERIAL LVDS SERIAL LVDS SERIAL LVDS D+A D-A D+B D-B D+C D-C D+D D-D D+E D-E D+F D-F D+G D-G D+H D-H APPLICATIONS Medical imaging and nondestructive ultrasound Portable ultrasound and digital beam forming systems Quadrature radio receivers Diversity radio receivers Tape drives Optical networking Test equipment FCO+ DATA RATE MULTIPLIER FCO- DCO+ DCO- 06296-001 RBIAS AGND CSB SDIO/ ODM SCLK/ DTP CLK+ CLK- Figure 1. GENERAL DESCRIPTION The AD9252 is an octal, 14-bit, 50 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit that is designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 50 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock (DCO) for capturing data on the output and a frame clock (FCO) for signaling a new output byte are provided. Individual channel power-down is supported and typically consumes less than 2 mW when all channels are disabled. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom userdefined test patterns entered via the serial port interface (SPI(R)). The AD9252 is available in a Pb-free, 64-lead LFCSP package. It is specified over the industrial temperature range of -40C to +85C. PRODUCT HIGHLIGHTS 1. 2. 3. 4. Small Footprint. Eight ADCs are contained in a small, spacesaving package; low power of 93.5 mW/channel at 50 MSPS. Ease of Use. A data clock output (DCO) operates up to 300 MHz and supports double data rate operation (DDR). User Flexibility. Serial port interface (SPI) control offers a wide range of flexible features to meet specific system requirements. Pin-Compatible Family. This includes the AD9212 (10-bit), and AD9222 (12-bit). One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved. AD9252 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 AC Specifications.......................................................................... 4 Digital Specifications ................................................................... 5 Switching Specifications .............................................................. 6 Timing Diagrams.............................................................................. 7 Absolute Maximum Ratings............................................................ 9 Thermal Impedance ..................................................................... 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 Equivalent Circuits ......................................................................... 12 Typical Performance Characteristics ........................................... 14 Theory of Operation ...................................................................... 17 Analog Input Considerations ................................................... 17 Clock Input Considerations...................................................... 19 Serial Port Interface (SPI).............................................................. 27 Hardware Interface..................................................................... 27 Memory Map .................................................................................. 29 Reading the Memory Map Table.............................................. 29 Reserved Locations .................................................................... 29 Default Values ............................................................................. 29 Logic Levels................................................................................. 29 Evaluation Board ............................................................................ 33 Power Supplies............................................................................ 33 Input Signals................................................................................ 33 Output Signals ............................................................................ 33 Default Operation and Jumper Selection Settings................. 34 Alternative Analog Input Drive Configuration...................... 35 Outline Dimensions ....................................................................... 52 Ordering Guide .......................................................................... 52 REVISION HISTORY 10/06--Revision 0: Initial Version Rev. 0 | Page 2 of 52 AD9252 SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = -0.5 dBFS, unless otherwise noted. Table 1. Parameter 1 RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error Reference Voltage (1 V Mode) REFERENCE Output Voltage Error (VREF = 1 V) Load Regulation @ 1.0 mA (VREF = 1 V) Input Resistance ANALOG INPUTS Differential Input Voltage Range (VREF = 1 V) Common-Mode Voltage Differential Input Capacitance Analog Bandwidth, Full Power POWER SUPPLY AVDD DRVDD IAVDD IDRVDD Total Power Dissipation (Including Output Drivers) Power-Down Dissipation Standby Dissipation 2 CROSSTALK CROSSTALK (Overrange Condition) 3 1 2 Temperature Min 14 AD9252-50 Typ Max Unit Bits Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full 1.7 1.7 Guaranteed 1 3 1.5 0.3 0.4 1.5 2 17 21 2 3 6 2 AVDD/2 7 325 1.8 1.8 360 55.5 748 2 89 -90 -90 8 8 2.5 0.7 1 4 mV mV % FS % FS LSB LSB ppm/C ppm/C ppm/C 30 mV mV k V p-p V pF MHz 1.9 1.9 373.4 58 773 11 V V mA mA mW mW mW dB dB See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. Can be controlled via SPI. 3 Overrange condition is specific with 6 dB of the full-scale input range. Rev. 0 | Page 3 of 52 AD9252 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = -0.5 dBFS, unless otherwise noted. Table 2. Parameter 1 SIGNAL-TO-NOISE RATIO (SNR) Temperature Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full 25C 25C Min AD9252-50 Typ Max 73.2 71 73 72.7 71 72.5 70.2 72.2 72 70.5 11.87 11.5 11.84 11.79 11.5 85 73 84 83 79 -85 -84 -73 -83 -79 -90 -90 -80 -90 -89 80.0 80.0 Unit dB dB dB dB dB dB dB dB Bits Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) EFFECTIVE NUMBER OF BITS (ENOB) SPURIOUS-FREE DYNAMIC RANGE (SFDR) WORST HARMONIC (Second or Third) WORST OTHER (Excluding Second or Third) TWO-TONE INTERMODULATION DISTORTION (IMD)-- AIN1 AND AIN2 = -7.0 dBFS fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz fIN1 = 15 MHz, fIN2 = 16 MHz fIN1 = 70 MHz, fIN2 = 71 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. Rev. 0 | Page 4 of 52 AD9252 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = -0.5 dBFS, unless otherwise noted. Table 3. Parameter 1 CLOCK INPUTS (CLK+, CLK-) Logic Compliance Differential Input Voltage 2 Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance LOGIC INPUTS (PDWN, SCLK/DTP) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (CSB) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (SDIO/ODM) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC OUTPUT (SDIO/ODM)3 Logic 1 Voltage (IOH = 800 A) Logic 0 Voltage (IOL = 50 A) DIGITAL OUTPUTS (D+, D-), (ANSI-644) Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) DIGITAL OUTPUTS (D+, D-), (Low Power, Reduced Signal Option) Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) 1 2 3 Temperature Min AD9252-50 Typ Max CMOS/LVDS/LVPECL Unit Full Full 25C 25C Full Full 25C 25C Full Full 25C 25C Full Full 25C 25C Full Full 250 1.2 20 1.5 1.2 30 0.5 1.2 70 0.5 1.2 0 30 2 1.79 0.05 LVDS DRVDD + 0.3 0.3 3.6 0.3 3.6 0.3 mV p-p V k pF V V k pF V V k pF V V k pF V V Full Full 247 1.125 454 1.375 Offset binary mV V LVDS Full Full 150 1.10 250 1.30 Offset binary mV V See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. This is specified for LVDS and LVPECL only. This is specified for 13 SDIO pins sharing the same connection. Rev. 0 | Page 5 of 52 AD9252 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = -0.5 dBFS, unless otherwise noted. Table 4. AD9252-50 Parameter 1 CLOCK 2 Maximum Clock Rate Minimum Clock Rate Clock Pulse Width High (tEH) Clock Pulse Width Low (tEL) OUTPUT PARAMETERS2, 3 Propagation Delay (tPD) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) FCO Propagation Delay (tFCO) DCO Propagation Delay (tCPD) 4 DCO to Data Delay (tDATA)4 DCO to FCO Delay (tFRAME)4 Data to Data Skew (tDATA-MAX - tDATA-MIN) Wake-Up Time (Standby) Wake-Up Time (Power-Down) Pipeline Latency APERTURE Aperture Delay (tA) Aperture Uncertainty (Jitter) Out-of-Range Recovery Time Temp Full Full Full Full Full Full Full Full Full Full Full Full 25C 25C Full Min 50 10 10.0 10.0 1.5 2.3 300 300 2.3 tFCO + (tSAMPLE/28) (tSAMPLE/28) (tSAMPLE/28) 50 600 375 8 3.1 Typ Max Unit MSPS MSPS ns ns ns ps ps ns ns ps ps ps ns s CLK cycles ps ps rms CLK cycles 1.5 3.1 (tSAMPLE/28) - 300 (tSAMPLE/28) - 300 (tSAMPLE/28) + 300 (tSAMPLE/28) + 300 200 25C 25C 25C 750 <1 1 1 2 3 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. Can be adjusted via the SPI interface. Measurements were made using a part soldered to FR4 material. 4 tSAMPLE/28 is based on the number of bits divided by 2 because the delays are based on half duty cycles. Rev. 0 | Page 6 of 52 AD9252 TIMING DIAGRAMS N-1 AIN tA N CLK- tEH tEL CLK+ tCPD DCO- DCO+ tFCO FCO- tFRAME FCO+ tPD D- MSB N-8 D+ D12 N-8 D11 N-8 D10 N-8 D9 N-8 tDATA 06296-003 D8 N-8 D7 N-8 D6 N-8 D5 N-8 D4 N-8 D3 N-8 D2 N-8 D1 N-8 D0 N-8 MSB N-7 D12 N-7 Figure 2. 14-Bit Data Serial Stream (Default) N-1 AIN tA N CLK- tEH tEL CLK+ tCPD DCO- DCO+ tFCO FCO- tFRAME FCO+ tPD D- MSB N-8 D10 N-8 D9 N-8 D8 N-8 D7 N-8 tDATA D6 N-8 D5 N-8 D4 N-8 D3 N-8 D2 N-8 D1 N-8 D0 N-8 MSB N-7 D10 N-7 D+ Figure 3. 12-Bit Data Serial Stream Rev. 0 | Page 7 of 52 06296-002 AD9252 N-1 AIN tA N tEH CLK- tEL CLK+ tCPD DCO- DCO+ tFCO FCO- tFRAME FCO+ tPD D- LSB N-8 D+ D0 N-8 D1 N-8 D2 N-8 D3 N-8 tDATA 06296-004 D4 N-8 D5 N-8 D6 N-8 D7 N-8 D8 N-8 D9 N-8 D10 N-8 D11 N-8 D12 N-8 LSB N-7 D0 N-7 Figure 4. 14-Bit Data Serial Stream, LSB First Rev. 0 | Page 8 of 52 AD9252 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter ELECTRICAL AVDD DRVDD AGND AVDD Digital Outputs (D+, D-, DCO+, DCO-, FCO+, FCO-) CLK+, CLK- VIN+, VIN- SDIO/ODM PDWN, SCLK/DTP, CSB REFT, REFB, RBIAS VREF, SENSE ENVIRONMENTAL Operating Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) With Respect To AGND DRGND DRGND DRVDD DRGND Rating -0.3 V to +2.0 V -0.3 V to +2.0 V -0.3 V to +0.3 V -2.0 V to +2.0 V -0.3 V to +2.0 V THERMAL IMPEDANCE Table 6. Air Flow Velocity (m/s) 0.0 1.0 2.5 1 JA1 17.7C/W 15.5C/W 13.9C/W JB 8.7C/W JC 0.6C/W JA for a 4-layer PCB with solid ground plane (simulated). Exposed pad soldered to PCB. AGND AGND AGND AGND AGND AGND -0.3 V to +3.9 V -0.3 V to +2.0 V -0.3 V to +2.0 V -0.3 V to +3.9 V -0.3 V to +2.0 V -0.3 V to +2.0 V -40C to +85C 150C 300C -65C to +150C ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 9 of 52 AD9252 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PIN 1 INDICATOR VIN+F VIN-F AVDD VIN-E VIN+E AVDD REFT REFB VREF SENSE RBIAS VIN+D VIN-D AVDD VIN-C VIN+C AVDD VIN+G VIN-G AVDD VIN-H VIN+H AVDD AVDD CLK- CLK+ AVDD AVDD DRGND DRVDD D-H D+H 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 EXPOSED PADDLE, PIN 0 (BOTTOM OF PACKAGE) AD9252 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AVDD VIN+B VIN-B AVDD VIN-A VIN+A AVDD PDWN CSB SDIO/ODM SCLK/DTP AVDD DRGND DRVDD D+A D-A 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Table 7. Pin Function Descriptions Pin No. 0 1, 4, 7, 8, 11, 12, 37, 42, 45, 48, 51, 59, 62 13, 36 14, 35 2 3 5 6 9 10 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Mnemonic AGND AVDD Description Analog Ground (Exposed Paddle) 1.8 V Analog Supply DRGND DRVDD VIN+G VIN-G VIN-H VIN+H CLK- CLK+ D-H D+H D-G D+G D-F D+F D-E D+E DCO- DCO+ FCO- FCO+ D-D D+D D-C D+C D-B D+B Digital Output Driver Ground 1.8 V Digital Output Driver Supply ADC G Analog Input--True ADC G Analog Input--Complement ADC H Analog Input--Complement ADC H Analog Input--True Input Clock--Complement Input Clock--True ADC H Digital Output--Complement ADC H True Digital Output--True ADC G Digital Output--Complement ADC G True Digital Output--True ADC F Digital Output--Complement ADC F True Digital Output--True ADC E Digital Output--Complement ADC E True Digital Output--True Data Clock Digital Output--Complement Data Clock Digital Output--True Frame Clock Digital Output--Complement Frame Clock Digital Output--True ADC D Digital Output--Complement ADC D True Digital Output--True ADC C Digital Output--Complement ADC C True Digital Output--True ADC B Digital Output--Complement ADC B True Digital Output--True Rev. 0 | Page 10 of 52 D-G D+G D-F D+F D-E D+E DCO- DCO+ FCO- FCO+ D-D D+D D-C D+C D-B D+B Figure 5. 64-Lead LFCSP Top View 06296-005 AD9252 Pin No. 33 34 38 39 40 41 43 44 46 47 49 50 52 53 54 55 56 57 58 60 61 63 64 Mnemonic D-A D+A SCLK/DTP SDIO/ODM CSB PDWN VIN+A VIN-A VIN-B VIN+B VIN+C VIN-C VIN-D VIN+D RBIAS SENSE VREF REFB REFT VIN+E VIN-E VIN-F VIN+F Description ADC A Digital Output--Complement ADC A True Digital Output--True Serial Clock/Digital Test Pattern Serial Data Input-Output/Output Driver Mode Chip Select Bar Power Down ADC A Analog Input--True ADC A Analog Input--Complement ADC B Analog Input--Complement ADC B Analog Input--True ADC C Analog Input--True ADC C Analog Input--Complement ADC D Analog Input--Complement ADC D Analog Input--True External Resistor to Set the Internal ADC Core Bias Current Reference Mode Selection Voltage Reference Input/Output Differential Reference (Negative) Differential Reference (Positive) ADC E Analog Input--True ADC E Analog Input--Complement ADC F Analog Input--Complement ADC F Analog Input--True Rev. 0 | Page 11 of 52 AD9252 EQUIVALENT CIRCUITS DRVDD V V D+ V VIN D- V 06296-006 DRGND Figure 6. Equivalent Analog Input Circuit Figure 9. Equivalent Digital Output Circuit 10 CLK 10k 1.25V 10k 10 CLK SCLK/DTP OR PDWN 1k 30k 06296-007 06296-009 Figure 7. Equivalent Clock Input Circuit Figure 10. Equivalent SCLK/DTP or PDWN Input Circuit RBIAS 100 SDIO/ODM 350 06296-008 Figure 8. Equivalent SDIO/ODM Input Circuit Figure 11. Equivalent RBIAS Circuit Rev. 0 | Page 12 of 52 06296-011 30k 06296-010 AD9252 AVDD 70k CSB 1k VREF 06296-012 6k Figure 12. Equivalent CSB Input Circuit Figure 14. Equivalent VREF Circuit SENSE 1k Figure 13. Equivalent SENSE Circuit 06296-013 Rev. 0 | Page 13 of 52 06296-014 AD9252 TYPICAL PERFORMANCE CHARACTERISTICS 0 -20 AIN = -0.5dBFS SNR = 73.71dB ENOB = 11.95 BITS SFDR = 85.86dBc AMPLITUDE (dBFS) AIN = -0.5dBFS SNR = 71.16dB ENOB = 11.53 BITS -20 SFDR = 72.92dBc -40 0 AMPLITUDE (dBFS) -40 -60 -60 -80 -80 -100 -100 06296-048 0 5 10 15 20 25 0 5 10 15 20 25 FREQUENCY (MHz) FREQUENCY (MHz) Figure 15. Single-Tone 32k FFT with fIN = 2.3 MHz, fSAMPLE = 50 MSPS Figure 18. Single-Tone 32k FFT with fIN = 120 MHz, fSAMPLE = 50 MSPS AIN = -0.5dBFS SNR = 72.98dB ENOB = 11.83 BITS -20 SFDR = 83.8dBc 0 90 SFDR 85 AMPLITUDE (dBFS) SNR/SFDR (dB) -40 80 -60 75 SNR -80 70 -100 65 06296-049 0 5 10 15 20 25 FREQUENCY (MHz) ENCODE (MSPS) Figure 16. Single-Tone 32k FFT with fIN = 35 MHz, fSAMPLE = 50 MSPS Figure 19. SNR/SFDR vs. fSAMPLE, fIN = 10.3 MHz, fSAMPLE = 50 MSPS 0 -20 AIN = -0.5dBFS SNR = 72.36dB ENOB = 11.73 BITS SFDR = 86.21dBc 90 85 SFDR AMPLITUDE (dBFS) SNR/SFDR (dB) -40 80 -60 75 SNR 70 -80 -100 65 06296-050 0 5 10 15 20 25 FREQUENCY (MHz) ENCODE (MSPS) Figure 17. Single-Tone 32k FFT with fIN = 70 MHz, fSAMPLE = 50 MSPS Rev. 0 | Page 14 of 52 Figure 20. SNR/SFDR vs. fSAMPLE, fIN = 19.7 MHz, fSAMPLE = 50 MSPS 06296-040 -120 60 10 15 20 25 30 35 40 45 50 06296-039 -120 60 10 15 20 25 30 35 40 45 50 06296-051 -120 -120 AD9252 90 80 SFDR AMPLITUDE (dBFS) 06296-041 AIN1 AND AIN2 = -7dBFS SFDR = 83.64dB IMD2 = 95.57dBc -20 IMD3 = 84.26dBc 0 70 SNR/SFDR (dB) 60 50 80dB REFERENCE 40 30 20 10 -60 SNR -40 -60 -80 -100 -50 -40 -30 -20 ANALOG INPUT LEVEL (dBFS) -10 0 -120 0 5 10 15 FREQUENCY (MHz) 20 25 Figure 21. SNR/SFDR vs. Analog Input Level, fIN = 10.3 MHz, fSAMPLE = 50 MSPS Figure 24. Two-Tone 32k FFT with fIN1 = 70 MHz and fIN2 = 71 MHz, fSAMPLE = 50 MSPS 90 80 SFDR 70 SNR/SFDR (dB) 90 85 SFDR SNR/SFDR (dB) 60 50 80dB REFERENCE 40 30 20 06296-042 80 75 SNR SNR 70 65 -50 -40 -30 -20 ANALOG INPUT LEVEL (dBFS) -10 0 1 10 100 ANALOG INPUT FREQUENCY (MHz) 1000 Figure 22. SNR/SFDR vs. Analog Input Level, fIN = 19.7 MHz, fSAMPLE = 50 MSPS Figure 25. SNR/SFDR vs. fIN, fSAMPLE = 50 MSPS 0 -20 AIN1 AND AIN2 = -7dBFS SFDR = 86.27dB IMD2 = 97.82dBc IMD3 = 86.13dBc 90 85 SFDR AMPLITUDE (dBFS) SINAD/SFDR (dB) -40 80 -60 75 SINAD 70 -80 -100 65 06296-043 0 5 10 15 FREQUENCY (MHz) 20 25 -20 0 20 40 TEMPERATURE (C) 60 80 Figure 23. Two-Tone 32k FFT with fIN1 = 15 MHz and fIN2 = 16 MHz, fSAMPLE = 50 MSPS Figure 26. SINAD/SFDR vs. Temperature, fIN = 19.7 MHz, fSAMPLE = 50 MSPS Rev. 0 | Page 15 of 52 06296-046 -120 60 -40 06296-045 10 -60 60 06296-044 AD9252 2.0 1.5 1.0 0.5 1.8 1.047LSB rms 1.6 NUMBER OF HITS (Millions) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 INL (LSB) 0 -0.5 -1.0 -1.5 -2.0 06296-053 0 2000 4000 6000 8000 CODE 10000 12000 14000 16000 N-3 N-2 N-1 N CODE N+ 1 N+2 N+3 Figure 27. INL, fIN = 2.3 MHz, fSAMPLE = 50 MSPS Figure 30. Input-Referred Noise Histogram, fSAMPLE = 50 MSPS 1.0 0.8 0.6 0 -20 NPR = 62.5dB NOTCH = 18.0MHz NOTCH WIDTH = 2.3MHz AMPLITUDE (dBFS) 0.4 DNL (LSB) -40 0.2 0 -0.2 -0.4 -0.6 -0.8 0 2000 4000 6000 8000 CODE 10000 12000 14000 16000 06296-052 -60 -80 -100 0 5 10 15 20 25 FREQUENCY (MHz) Figure 28. DNL, fIN = 2.3 MHz, fSAMPLE = 50 MSPS Figure 31. Noise Power Ratio (NPR), fSAMPLE = 50 MSPS -30 -35 -40 0 -1 -2 -3 AMPLITUDE (dBFS) -3dB BANDWIDTH = 325MHz CMRR (dB) -45 -50 -55 -60 -65 -70 -4 -5 -6 -7 -8 -9 -10 06296-055 0 5 10 15 20 25 30 35 40 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY (MHz) FREQUENCY (MHz) Figure 29. CMRR vs. Frequency, fSAMPLE = 50 MSPS Figure 32. Full Power Bandwidth vs. Frequency, fSAMPLE = 50 MSPS Rev. 0 | Page 16 of 52 06296-037 -11 06296-038 -1.0 -120 06296-054 0 AD9252 THEORY OF OPERATION The AD9252 architecture consists of a pipelined ADC that is divided into three sections: a 4-bit first stage followed by eight 1.5-bit stages and a final 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stages. The quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample while the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The output staging block aligns the data, carries out the error correction, and passes the data to the output buffers. The data is then serialized and aligned to the frame and output clock. realizing the maximum bandwidth of the ADC. Such use of low-Q inductors or ferrite beads is required when driving the converter front end at high IF frequencies. Either a shunt capacitor or two single-ended capacitors can be placed on the inputs to provide a matching passive network. This ultimately creates a low-pass filter at the input to limit any unwanted broadband noise. See the AN-742 Application Note, the AN-827 Application Note, and the Analog Dialogue article "Transformer-Coupled Front-End for Wideband A/D Converters" for more information on this subject. In general, the precise values depend on the application. The analog inputs of the AD9252 are not internally dc-biased. In ac-coupled applications, the user must provide this bias externally. Setting the device so that VCM = AVDD/2 is recommended for optimum performance, but the device can function over a wider range with reasonable performance, as shown in Figure 34 and Figure 35. 90 SFDR (dBc) ANALOG INPUT CONSIDERATIONS The analog input to the AD9252 is a differential switched-capacitor circuit designed for processing differential input signals. The input can support a wide common-mode range and maintain excellent performance. An input common-mode voltage of midsupply minimizes signal-dependent errors and provides optimum performance. SNR/SFDR (dB) 85 80 75 70 SNR (dB) 65 CPAR VIN+ S S ANALOG INPUT COMMON-MODE VOLTAGE (V) H CSAMPLE S S 90 Figure 34. SNR/SFDR vs. Common-Mode Voltage, fIN = 2.3 MHz, fSAMPLE = 50 MSPS CSAMPLE VIN- CPAR H H 06296-017 85 SFDR (dBc) Figure 33. Switched-Capacitor Input Circuit SNR/SFDR (dB) 80 75 SNR (dB) 70 The clock signal alternately switches the input circuit between sample mode and hold mode (see Figure 33). When the input circuit is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current injected from the output stage of the driving source. In addition, low-Q inductors or ferrite beads can be placed on each leg of the input to reduce the high differential capacitance seen at the analog inputs, thus 65 ANALOG INPUT COMMON-MODE VOLTAGE (V) Figure 35. SNR/SFDR vs. Common-Mode Voltage, fIN = 35 MHz, fSAMPLE = 50 MSPS Rev. 0 | Page 17 of 52 06296-057 60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 06296-056 H 60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 AD9252 For best dynamic performance, the source impedances driving VIN+ and VIN- should be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal reference buffer creates the positive and negative reference voltages, REFT and REFB, respectively, that define the span of the ADC core. The output common mode of the reference buffer is set to midsupply, and the REFT and REFB voltages and span are defined as REFT = 1/2 (AVDD + VREF) REFB = 1/2 (AVDD - VREF) Span = 2 x (REFT - REFB) = 2 x VREF It can be seen from these equations that the REFT and REFB voltages are symmetrical about the midsupply voltage and, by definition, the input span is twice the value of the VREF voltage. Maximum SNR performance is always achieved by setting the ADC to the largest span in a differential configuration. In the case of the AD9252, the largest input span available is 2 V p-p. ADT1-1WT 1:1 Z RATIO R C VIN+ 2V p-p 49.9 AVDD 1k 1k CDIFF1 R C ADC AD9252 VIN- AGND 1C DIFF IS OPTIONAL. Figure 36. Differential Transformer-Coupled Configuration for Baseband Applications 2V p-p 16nH 65 ADT1-1WT 0.1F 1:1 Z RATIO 16nH 499 16nH AVDD 1k 1k 06296-019 33 2.2pF 33 1k VIN+ ADC AD9252 VIN- 0.1F Differential Input Configurations There are several ways in which to drive the AD9252 either actively or passively. In either case, the optimum performance is achieved by driving the analog input differentially. One example is by using the AD8334 differential driver. It provides excellent performance and a flexible interface to the ADC (see Figure 39) for baseband applications. This configuration is common for medical ultrasound systems. However, the noise performance of most amplifiers is not adequate to achieve the true performance of the AD9252. For applications where SNR is a key parameter, differential transformer coupling is the recommended input configuration. Two examples are shown in Figure 36 and Figure 37. In any configuration, the value of the shunt capacitor, C, is dependent on the input frequency and may need to be reduced or removed. Figure 37. Differential Transformer-Coupled Configuration for IF Applications Single-Ended Input Configuration A single-ended input may provide adequate performance in cost-sensitive applications. In this configuration, SFDR and distortion performance degrade due to the large input commonmode swing. If the application requires a single-ended input configuration, ensure that the source impedances on each input are well matched in order to achieve the best possible performance. A full-scale input of 2 V p-p can still be applied to the ADC's VIN+ pin while the VIN- pin is terminated. Figure 38 details a typical single-ended input configuration. AVDD C R 2V p-p 49.9 0.1F 1k AVDD 1k 25 0.1F 1C DIFF IS OPTIONAL. VIN+ CDIFF1 R C ADC AD9252 VIN- 06296-020 1k Figure 38. Single-Ended Input Configuration 0.1F LOP 0.1F 120nH 1V p-p 22pF VIP VOH 187 0.1F 1.0k VGA 374 1.0k R C R INH AD8334 LNA LMD VIN+ ADC AD9252 VIN- 10F 06296-021 0.1F VOL LON VIN 187 VREF 0.1F 0.1F 18nF 274 0.1F Figure 39. Differential Input Configuration Using the AD8334 Rev. 0 | Page 18 of 52 06296-018 0.1F AD9252 CLOCK INPUT CONSIDERATIONS For optimum performance, the AD9252 sample clock inputs (CLK+ and CLK-) should be clocked with a differential signal. This signal is typically ac-coupled into the CLK+ and CLK- pins via a transformer or capacitors. These pins are biased internally and require no additional bias. Figure 40 shows one preferred method for clocking the AD9252. The low jitter clock source is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the secondary transformer limit clock excursions into the AD9252 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9252 and preserves the fast rise and fall times of the signal, which are critical to low jitter performance. MINI-CIRCUITS ADT1-1WT, 1:1Z 0.1F XFMR 100 0.1F 0.1F SCHOTTKY DIODES: HSM2812 In some applications, it is acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, CLK+ should be directly driven from a CMOS gate, and the CLK- pin should be bypassed to ground with a 0.1 F capacitor in parallel with a 39 k resistor (see Figure 43). Although the CLK+ input circuit supply is AVDD (1.8 V), this input is designed to withstand input voltages up to 3.3 V, making the selection of the drive logic voltage very flexible. 0.1F CLOCK INPUT CLK AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 OPTIONAL 0.1F 100 501 CMOS DRIVER CLK CLK+ 0.1F ADC AD9252 CLK- 06296-025 0.1F 150 RESISTOR IS OPTIONAL. 39k Figure 43. Single-Ended 1.8 V CMOS Sample Clock CLK+ 0.1F CLOCK INPUT 50 ADC AD9252 06296-022 CLK- CLOCK INPUT 0.1F CLK AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 OPTIONAL 0.1F 100 501 CMOS DRIVER CLK CLK+ Figure 40. Transformer-Coupled Differential Clock 0.1F 0.1F ADC AD9252 06296-026 CLK- If a low jitter clock is available, another option is to ac-couple a differential PECL signal to the sample clock input pins as shown in Figure 41. The AD9510/AD9511/AD9512/AD9513/AD9514/ AD9515 family of clock drivers offers excellent jitter performance. AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 CLOCK INPUT 0.1F CLK PECL DRIVER CLK 501 501 OPTIONAL. 240 240 06296-023 150 RESISTOR IS OPTIONAL. Figure 44. Single-Ended 3.3 V CMOS Sample Clock Clock Duty Cycle Considerations Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9252 contains a duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9252. When the DCS is on, noise and distortion performance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS function to be off. If so, keep in mind that the dynamic range performance can be affected when operated in this mode. See the Memory Map section for more details on using this feature. The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately eight clock cycles to allow the DLL to acquire and lock to the new rate. 0.1F CLK+ 100 0.1F CLOCK INPUT 0.1F ADC AD9252 CLK- 150 RESISTORS ARE Figure 41. Differential PECL Sample Clock AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 0.1F CLK LVDS DRIVER CLK 501 501 06296-024 CLOCK INPUT 0.1F CLK+ 100 0.1F CLOCK INPUT 0.1F ADC AD9252 CLK- 150 RESISTORS ARE OPTIONAL. Figure 42. Differential LVDS Sample Clock Rev. 0 | Page 19 of 52 AD9252 Clock Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated by SNR degradation = 20 x log 10 [1/2 x x fA x tJ] In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter specifications. IF undersampling applications are particularly sensitive to jitter (see Figure 45). CURRENT (A) Power Dissipation and Power-Down Mode As shown in Figure 46, the power dissipated by the AD9252 is proportional to its sample rate. The digital power dissipation does not vary much because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers. 0.40 0.35 0.30 AVDD CURRENT 0.25 0.20 0.15 0.10 0.05 0 10 DRVDD CURRENT 0.55 0.70 0.80 0.75 15 20 25 30 35 40 45 50 Refer to the AN-501 Application Note and the AN-756 Application Note for more in-depth information about jitter performance as it relates to ADCs (visit www.analog.com). 130 120 110 100 16 BITS 14 BITS 12 BITS 10 BITS 8 BITS 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps 10 100 ANALOG INPUT FREQUENCY (MHz) 1000 06296-015 ENCODE (MSPS) Figure 46. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, fSAMPLE = 50 MSPS RMS CLOCK JITTER REQUIREMENT SNR (dB) 90 80 70 60 50 40 30 1 Figure 45. Ideal SNR vs. Input Frequency and Jitter Rev. 0 | Page 20 of 52 06296-062 The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9252. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. TOTAL POWER 0.65 0.60 0.50 POWER (W) AD9252 By asserting the PDWN pin high, the AD9252 is placed in power-down mode. In this state, the ADC typically dissipates 11 mW. During power-down, the LVDS output drivers are placed in a high impedance state. The AD9252 returns to normal operating mode when the PDWN pin is pulled low. This pin is both 1.8 V and 3.3 V tolerant. In power-down mode, low power dissipation is achieved by shutting down the reference, reference buffer, PLL, and biasing networks. The decoupling capacitors on REFT and REFB are discharged when entering power-down mode and must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in the power-down mode; shorter cycles result in proportionally shorter wake-up times. With the recommended 0.1 F and 4.7 F decoupling capacitors on REFT and REFB, it takes approximately 1 sec to fully discharge the reference buffer decoupling capacitors and 375 s to restore full operation. There are a number of other power-down options available when using the SPI port interface. The user can individually power down each channel or put the entire device into standby mode. This allows the user to keep the internal PLL powered when fast wake-up times (~600 ns) are required. See the Memory Map section for more details on using these features. 100 termination resistor placed as close to the receiver as possible. No far-end receiver termination and poor differential trace routing may result in timing errors. It is recommended that the trace length is no longer than 24 inches and that the differential output traces are kept close together and at equal lengths. An example of the FCO and data stream with proper trace length and position can be found in Figure 47. Figure 47. LVDS Output Timing Example in ANSI Mode (Default) Digital Outputs and Timing The AD9252 differential outputs conform to the ANSI-644 LVDS standard on default power-up. This can be changed to a low power, reduced signal option similar to the IEEE 1596.3 standard using the SDIO/ODM pin or via the SPI. This LVDS standard can further reduce the overall power dissipation of the device by approximately 36 mW. See the SDIO/ODM Pin section or Table 15 in the Memory Map section for more information. The LVDS driver current is derived on-chip and sets the output current at each output equal to a nominal 3.5 mA. A 100 differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver. The AD9252 LVDS outputs facilitate interfacing with LVDS receivers in custom ASICs and FPGAs that have LVDS capability for superior switching performance in noisy environments. Single point-to-point net topologies are recommended with a An example of the LVDS output using the ANSI standard (default) data eye and a time interval error (TIE) jitter histogram with trace lengths less than 24 inches on regular FR-4 material is shown in Figure 48. Figure 49 shows an example of when the trace lengths exceed 24 inches on regular FR-4 material. Notice that the TIE jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position. It is up to the user to determine if the waveforms meet the timing budget of the design when the trace lengths exceed 24 inches. Additional SPI options allow the user to further increase the internal termination (increasing the current) of all eight outputs in order to drive longer trace lengths (see Figure 50). Even though this produces sharper rise and fall times on the data edges and is less prone to bit errors, the power dissipation of the DRVDD supply increases when this option is used. Also notice in Figure 50 that the histogram has improved. In cases that require increased driver strength to the DCO and FCO outputs because of load mismatch, Register 15 allows the user to increase the drive strength by 2x. To do this, set the appropriate bit in Register 5. Note that this feature cannot be used with Bit 4 and Bit 5 in Register 15. Bit 4 and Bit 5 will take precedence over this feature. See the Memory Map section for more details. Rev. 0 | Page 21 of 52 06296-027 CH1 500mV/DIV = FCO CH2 500mV/DIV = DCO CH3 500mV/DIV = DATA 5.0ns/DIV AD9252 500 400 300 200 100 0 -100 -200 -300 -400 -500 -1.5ns -1.0ns -0.5ns 0ns 0.5ns 1.0ns 1.5ns EYE DIAGRAM VOLTAGE (mV) EYE: ALL BITS ULS: 12071/12071 400 300 200 100 0 -100 -200 -300 -400 -1.5ns EYE: ALL BITS ULS: 12072/12072 EYE DIAGRAM VOLTAGE (mV) -1.0ns -0.5ns 0ns 0.5ns 1.0ns 1.5ns 90 80 70 60 50 40 30 20 10 06296-030 80 70 TIE JITTER HISTOGRAM (Hits) TIE JITTER HISTOGRAM (Hits) 60 50 40 30 20 10 0 -150ps 06296-029 0 -150ps -100ps -50ps 0ps 50ps 100ps 150ps -100ps -50ps 0ps 50ps 100ps 150ps Figure 48. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths Less than 24 Inches on Standard FR-4 500 400 EYE DIAGRAM VOLTAGE (mV) Figure 50. Data Eye for LVDS Outputs in ANSI Mode with 100 Termination on and Trace Lengths Greater than 24 Inches on Standard FR-4 EYE: ALL BITS ULS: 12067/12067 300 200 100 0 -100 -200 -300 -400 -500 -1.5ns -1.0ns -0.5ns 0ns 0.5ns 1.0ns 1.5ns The format of the output data is offset binary by default. An example of the output coding format can be found in Table 8. If it is desired to change the output data format to twos complement, see the Memory Map section. Table 8. Digital Output Coding Code 16383 8192 8191 0 (VIN+) - (VIN-), Input Span = 2 V p-p (V) +1.00 0.00 -0.000122 -1.00 Digital Output Offset Binary (D13 ... D0) 11 1111 1111 1111 10 0000 0000 0000 01 1111 1111 1111 00 0000 0000 0000 100 90 TIE JITTER HISTOGRAM (Hits) 80 70 60 50 40 30 20 10 0 -200ps -100ps 0ps 100ps 200ps 06296-028 Data from each ADC is serialized and provided on a separate channel. The data rate for each serial stream is equal to 14 bits times the sample clock rate, with a maximum of 700 Mbps (14 bits x 50 MSPS = 700 Mbps). The lowest typical conversion rate is 10 MSPS. However, if lower sample rates are required for a specific application, the PLL can be set up for encode rates lower than 10 MSPS via the SPI. This allows encode rates as low as 5 MSPS. See the Memory Map section to enable this feature. Figure 49. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths Greater than 24 Inches on Standard FR-4 Rev. 0 | Page 22 of 52 AD9252 Two output clocks are provided to assist in capturing data from the AD9252. The DCO is used to clock the output data and is equal to seven times the sampling clock (CLK) rate. Data is clocked out of the AD9252 and must be captured on the rising and falling edges of the DCO that supports double data rate Table 9. Flex Output Test Modes Output Test Mode Bit Sequence 0000 0001 Subject to Data Format Select N/A Yes (DDR) capturing. The frame clock out (FCO) is used to signal the start of a new output byte and is equal to the sampling clock rate. See the timing diagram shown in Figure 2 for more information. Pattern Name Off (default) Midscale short 0010 +Full-scale short 0011 -Full-scale short 0100 Checker board 0101 0110 0111 PN sequence long 1 PN sequence short1 One/zero word toggle 1000 1001 User input One/zero bit toggle 1010 1x sync 1011 One bit high 1100 Mixed frequency Digital Output Word 1 N/A 1000 0000 (8-bit) 10 0000 0000 (10-bit) 1000 0000 0000 (12-bit) 10 0000 0000 0000 (14-bit) 1111 1111 (8-bit) 11 1111 1111 (10-bit) 1111 1111 1111 (12-bit) 11 1111 1111 1111 (14-bit) 0000 0000 (8-bit) 00 0000 0000 (10-bit) 0000 0000 0000 (12-bit) 00 0000 0000 0000 (14-bit) 1010 1010 (8-bit) 10 1010 1010 (10-bit) 1010 1010 1010 (12-bit) 10 1010 1010 1010 (14-bit) N/A N/A 1111 1111 (8-bit) 11 1111 1111 (10-bit) 1111 1111 1111 (12-bit) 11 1111 1111 1111 (14-bit) Register 0x19 to Register 0x1A 1010 1010 (8-bit) 10 1010 1010 (10-bit) 1010 1010 1010 (12-bit) 10 1010 1010 1010 (14-bit) 0000 1111 (8-bit) 00 0001 1111 (10-bit) 0000 0011 1111 (12-bit) 00 0000 0111 1111 (14-bit) 1000 0000 (8-bit) 10 0000 0000 (10-bit) 1000 0000 0000 (12-bit) 10 0000 0000 0000 (14-bit) 1010 0011 (8-bit) 10 0110 0011 (10-bit) 1010 0011 0011 (12-bit) 10 1000 0110 0111 (14-bit) Digital Output Word 2 N/A Same Same Yes Same Yes 0101 0101 (8-bit) 01 0101 0101 (10-bit) 0101 0101 0101 (12-bit) 01 0101 0101 0101 (14-bit) N/A N/A 0000 0000 (8-bit) 00 0000 0000 (10-bit) 0000 0000 0000 (12-bit) 00 0000 0000 0000 (14-bit) Register 0x1B to Register 0x1C N/A No Yes Yes No No No N/A No N/A No N/A No 1 PN, or pseudorandom number, sequence is determined by the number of bits in the shift register. The long sequence is 23 bits and the short sequence is 9 bits. How the sequence is generated and utilized is described in the ITU O.150 standard. In general, the polynomial, X23 + X18 + 1 (long) and X9 + X5 + 1 (short), defines the pseudorandom sequence. Rev. 0 | Page 23 of 52 AD9252 When using the serial port interface (SPI), the DCO phase can be adjusted in 60 increments relative to the data edge. This enables the user to refine system timing margins if required. The default DCO timing, as shown in Figure 2, is 90 relative to the output data edge. An 8-, 10-, and 12-bit serial stream can also be initiated from the SPI. This allows the user to implement and test compatibility to lower resolution systems. When changing the resolution to an 8-, 10-, or 12-bit serial stream, the data stream is shortened. See Figure 3 for a 12-bit example. When using the SPI, all of the data outputs can also be inverted from their nominal state. This is not to be confused with inverting the serial stream to an LSB-first mode. In default mode, as shown in Figure 2, the MSB is represented first in the data output serial stream. However, this can be inverted so that the LSB is represented first in the data output serial stream (see Figure 4). There are 12 digital output test pattern options available that can be initiated through the SPI. This is a useful feature when validating receiver capture and timing. Refer to Table 9 for the output bit sequencing options available. Some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern chosen. It should be noted that some patterns may not adhere to the data format select option. In addition, customer user patterns can be assigned in the 0x19, 0x1A, 0x1B, and 0x1C register addresses. All test mode options can support 8- to 14-bit word lengths in order to verify data capture to the receiver. Please consult the Memory Map section for information on how to change these additional digital output timing features through the serial port interface or SPI. Table 10. Output Driver Mode Pin Settings Selected ODM Normal Operation ODM ODM Voltage 10 k to AGND AVDD Resulting Output Standard ANSI-644 (default) Resulting FCO and DCO ANSI-644 (default) Low power, reduced signal option Low power, reduced signal option SCLK/DTP Pin For applications that do not require SPI mode operation, the serial clock/digital test pattern (SCLK/DTP) pin can enable a single digital test pattern if this pin and the CSB pin are held high during device power-up. When the DTP is tied to AVDD, all the ADC channel outputs shift out the following pattern: 10 0000 0000 0000. The FCO and DCO outputs still work as usual while all channels shift out the repeatable test pattern. This pattern allows the user to perform timing alignment adjustments among the FCO, DCO, and output data. For normal operation, this pin should be tied to AGND through a 10 k resistor. This pin is both 1.8 V and 3.3 V tolerant. Table 11. Digital Test Pattern Pin Settings Selected DTP Normal Operation DTP DTP Voltage 10 k to AGND AVDD Resulting D+ and D- Normal operation 10 0000 0000 0000 Resulting FCO and DCO Normal operation Normal operation Additional and custom test patterns can also be observed when commanded from the SPI port. Consult the Memory Map section to choose from the different options available. SDIO/ODM Pin For applications that do not require SPI mode operation, the SDIO/ODM pin can enable a low power, reduced signal option similar to the IEEE 1596.3 reduced range link output standard if this pin and the CSB pin are tied to AVDD during device powerup. This option should only be used when the digital output trace lengths are less than 2 inches from the LVDS receiver. The FCO, DCO, and outputs function normally, but the LVDS signal swing of all channels is reduced from 350 mV p-p to 200 mV p-p. This output mode allows the user to further lower the power on the DRVDD supply. For applications where this pin is not used, it should be tied low. In this case, the device pin can be left open, and the 30 k internal pull-down resistor pulls this pin low. This pin is only 1.8 V tolerant. If applications require this pin to be driven from a 3.3 V logic level, insert a 1 k resistor in series with this pin to limit the current. CSB Pin The chip select bar (CSB) pin should be tied to AVDD for applications that do not require SPI mode operation. By tying CSB high, all SCLK and SDIO information is ignored. This pin is both 1.8 V and 3.3 V tolerant. RBIAS Pin To set the internal core bias current of the ADC, place a resistor (nominally equal to 10.0 k) to ground at the RBIAS pin. The resistor current is derived on-chip and sets the ADC's AVDD current to a nominal 360 mA at 50 MSPS. Therefore, it is imperative that at least a 1% tolerance on this resistor be used to achieve consistent performance. If SFDR performance is not as critical as power, simply adjust the ADC core current to achieve a lower power. Figure 51 and Figure 52 show the relationship between the dynamic range and power as the RBIAS resistance is changed. Nominally, a 10.0 k value is used, as indicated by the dashed line. Rev. 0 | Page 24 of 52 AD9252 90 Internal Reference Operation A comparator within the AD9252 detects the potential at the SENSE pin and configures the reference. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 53), setting VREF to 1 V. The REFT and REFB pins establish their input span of the ADC core from the reference configuration. The analog input fullscale range of the ADC equals twice the voltage at the reference pin for either an internal or an external reference configuration. If the reference of the AD9252 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 55 depicts how the internal reference voltage is affected by loading. VIN+ VIN- REFT ADC CORE 0.1F 0.1F REFB VREF 1F 0.1F SELECT LOGIC SENSE 0.5V 0.1F + 85 SFDR SNR/SFDR (dB) 80 75 70 SNR 65 RBIAS (k) Figure 51. SNR/SFDR vs. RBIAS 1.0 0.9 0.8 0.7 IAVDD (A) 06296-058 60 0 5 10 15 20 25 2.2F 0.6 0.5 0.4 0.3 0.2 0.1 06296-063 0 0 5 10 15 20 25 RBIAS (k) Figure 52. IAVDD vs. RBIAS Figure 53. Internal Reference Configuration VIN+ VIN- REFT ADC CORE EXTERNAL REFERENCE VREF 1F1 0.1F1 AVDD SENSE SELECT LOGIC 0.5V 0.1F 0.1F REFB 0.1F + Voltage Reference A stable and accurate 0.5 V voltage reference is built into the AD9252. This is gained up by a factor of 2 internally, setting VREF to 1.0 V, which results in a full-scale differential input span of 2 V p-p. The VREF is set internally by default; however, the VREF pin can be driven externally with a 1.0 V reference to achieve more accuracy. When applying the decoupling capacitors to the VREF, REFT, and REFB pins, use ceramic low ESR capacitors. These capacitors should be close to the ADC pins and on the same layer of the PCB as the AD9252. The recommended capacitor values and configurations for the AD9252 reference pin can be found in Figure 53. Table 12. Reference Settings Selected Mode External Reference Internal, 2 V p-p FSR SENSE Voltage AVDD AGND to 0.2 V Resulting VREF (V) N/A 1.0 Resulting Differential Span (V p-p) 2 x external reference 2.0 2.2F 1OPTIONAL. Figure 54. External Reference Operation Rev. 0 | Page 25 of 52 06296-032 06296-031 AD9252 External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift characteristics. Figure 56 shows the typical drift characteristics of the internal reference in 1 V mode. When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. The external reference is loaded with an equivalent 6 k load. An internal reference buffer generates the positive and negative full-scale references, REFT and REFB, for the ADC core. Therefore, the external reference must be limited to a nominal of 1.0 V. 5 0 -5 VREF ERROR (%) 0.02 0 -0.02 -0.04 VREF ERROR (%) -0.06 -0.08 -0.10 -0.12 -0.14 -0.16 -20 0 20 40 60 80 06296-060 -0.18 -40 TEMPERATURE (C) Figure 56. Typical VREF Drift -10 -15 -20 -25 -30 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 CURRENT LOAD (mA) Figure 55. VREF Accuracy vs. Load 06296-061 Rev. 0 | Page 26 of 52 AD9252 SERIAL PORT INTERFACE (SPI) The AD9252 serial port interface allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. This gives the user added flexibility and customization depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided down into fields, as documented in the Memory Map section. Detailed operational information can be found in the Analog Devices, Inc., user manual Interfacing to High Speed ADCs via SPI. There are three pins that define the serial port interface, or SPI, to this particular ADC. They are the SCLK, SDIO, and CSB pins. The SCLK (serial clock) is used to synchronize the read and write data presented to the ADC. The SDIO (serial data input/output) is a dual-purpose pin that allows data to be sent to and read from the internal ADC memory map registers. The CSB (chip select bar) is an active low control that enables or disables the read and write cycles (see Table 13). Table 13. Serial Port Pins Pin SCLK SDIO Function Serial Clock. The serial shift clock in. SCLK is used to synchronize serial interface reads and writes. Serial Data Input/Output. A dual-purpose pin. The typical role for this pin is an input or output, depending on the instruction sent and the relative position in the timing frame. Chip Select Bar (Active Low). This control gates the read and write cycles. In addition to the operation modes, the SPI port can be configured to operate in different manners. For applications that do not require a control port, the CSB line can be tied and held high. This places the remainder of the SPI pins in their secondary mode as defined in the Serial Port Interface (SPI) section. CSB can also be tied low to enable 2-wire mode. When CSB is tied low, SCLK and SDIO are the only pins required for communication. Although the device is synchronized during power-up, caution must be exercised when using this mode to ensure that the serial port remains synchronized with the CSB line. When operating in 2-wire mode, it is recommended to use a 1-, 2-, or 3-byte transfer exclusively. Without an active CSB line, streaming mode can be entered but not exited. In addition to word length, the instruction phase determines if the serial frame is a read or write operation, allowing the serial port to be used to both program the chip and read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the serial data input/output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. Data can be sent in MSB- or LSB-first mode. MSB-first mode is the default at power-up and can be changed by adjusting the configuration register. For more information about this and other features, see the user manual Interfacing to High Speed ADCs via SPI. CSB HARDWARE INTERFACE The pins described in Table 13 compose the physical interface between the user's programming device and the serial port of the AD9252. The SCLK and CSB pins function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. If multiple SDIO pins share a common connection, care should be taken to ensure that proper VOH levels are met. Assuming the same load as the AD9252, Figure 57 shows the number of SDIO pins that can be connected together and the resulting VOH level. 1.800 1.795 1.790 1.785 1.780 1.775 1.770 1.765 1.760 1.755 1.750 1.745 1.740 1.735 1.730 1.725 1.720 1.715 0 10 20 30 40 50 60 70 80 90 100 NUMBER OF SDIO PINS CONNECTED TOGETHER Figure 57. SDIO Pin Loading Rev. 0 | Page 27 of 52 06296-059 The falling edge of the CSB in conjunction with the rising edge of the SCLK determines the start of the framing sequence. During an instruction phase, a 16-bit instruction is transmitted, followed by one or more data bytes, which is determined by Bit Fields W0 and W1. An example of the serial timing and its definitions can be found in Figure 58 and Table 14. In normal operation, CSB is used to signal to the device that SPI commands are to be received and processed. When CSB is brought low, the device processes SCLK and SDIO to process instructions. Normally, CSB remains low until the communication cycle is complete. However, if connected to a slow device, CSB can be brought high between bytes, allowing older microcontrollers enough time to transfer data into shift registers. CSB can be stalled when transferring one, two, or three bytes of data. When W0 and W1 are set to 11, the device enters streaming mode and continues to process data, either reading or writing, until the CSB is taken high to end the communication cycle. This allows complete memory transfers without having to provide additional instructions. Regardless of the mode, if CSB is taken high in the middle of any byte transfer, the SPI state machine is reset and the device waits for a new instruction. VOH AD9252 This interface is flexible enough to be controlled by either serial PROMS or PIC mirocontrollers. This provides the user an alternative method, other than a full SPI controller, to program the ADC (see the AN-812 Application Note). If the user chooses not to use the SPI interface, these pins serve a dual function and are associated with secondary functions when the CSB is strapped to AVDD during device power-up. See the Theory of Operation section for details on which pinstrappable functions are supported on the SPI pins. tDS tS CSB tHI tDH tLO tCLK tH SCLK DON'T CARE DON'T CARE SDIO DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON'T CARE Figure 58. Serial Timing Details Table 14. Serial Timing Definitions Parameter tDS tDH tCLK tS tH tHI tLO tEN_SDIO tDIS_SDIO Timing (minimum, ns) 5 2 40 5 2 16 16 1 5 Description Set-up time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the clock Set-up time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK should be in a logic high state Minimum period that SCLK should be in a logic low state Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 58) Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 58) Rev. 0 | Page 28 of 52 06296-033 AD9252 MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map table has eight address locations. The memory map is roughly divided into three sections: chip configuration register map (Address 0x00 to Address 0x02), device index and transfer register map (Address 0x05 and Address 0xFF), and program register map (Address 0x08 to Address 0x25). The left-hand column of the memory map indicates the register address number in hexadecimal. The default value of this address is shown in hexadecimal in the right-hand column. The Bit 7 (MSB) column is the start of the default hexadecimal value given. For example, Hexadecimal Address 0x09, Clock, has a hexadecimal default value of 0x01. This means Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. This setting is the default for the duty cycle stabilizer in the on condition. By writing a 0 to Bit 6 at this address, the duty cycle stabilizer turns off. For more information on this and other functions, consult the user manual Interfacing to High Speed ADCs via SPI. RESERVED LOCATIONS Undefined memory locations should not be written to except when writing the default values suggested in this data sheet. Addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up. DEFAULT VALUES Coming out of reset, critical registers are preloaded with default values. These values are indicated in Table 15, where an X refers to an undefined feature. LOGIC LEVELS An explanation of various registers follows: "Bit is set" is synonymous with "bit is set to Logic 1" or "writing Logic 1 for the bit." Similarly, "clear a bit" is synonymous with "bit is set to Logic 0" or "writing Logic 0 for the bit." Rev. 0 | Page 29 of 52 AD9252 Table 15. Memory Map Register Addr. Bit 7 (Hex) Parameter Name (MSB) Chip Configuration Registers 00 chip_port_config 0 Bit 6 LSB first 1 = on 0 = off (default) Bit 5 Soft reset 1 = on 0 = off (default) Bit 4 1 Bit 3 1 Bit 2 Soft reset 1 = on 0 = off (default) Bit 1 LSB first 1 = on 0 = off (default) Bit 0 (LSB) 0 Default Value (Hex) 0x18 Default Notes/ Comments The nibbles should be mirrored so that LSB- or MSB-first mode registers correctly regardless of shift mode. Default is unique chip ID, different for each device. This is a readonly register. Child ID used to differentiate graded devices. Bits are set to determine which on-chip device receives the next write command. Bits are set to determine which on-chip device receives the next write command. Synchronously transfers data from the master shift register to the slave. Determines various generic modes of chip operation. Turns the internal duty cycle stabilizer on and off. 01 chip_id 8-bit Chip ID Bits 7:0 (AD9252 = 0x09), (default) Read only 02 chip_grade X Child ID 6:4 (identify device variants of Chip ID) 011 = 50 MSPS X X X X X X X Read only Device Index and Transfer Registers 04 device_index_2 X 05 device_index_1 X X FF device_update X X Clock Channel DCO 1 = on 0 = off (default) X Clock Channel FCO 1 = on 0 = off (default) X Data Channel H 1 = on (default) 0 = off Data Channel D 1 = on (default) 0 = off X Data Channel G 1 = on (default) 0 = off Data Channel C 1 = on (default) 0 = off X Data Channel F 1 = on (default) 0 = off Data Channel B 1 = on (default) 0 = off X Data Channel E 1 = on (default) 0 = off Data Channel A 1 = on (default) 0 = off SW transfer 1 = on 0 = off (default) 0x0F 0x0F 0x00 ADC Functions 08 modes X X X X X 09 clock X X X X X Internal power-down mode 000 = chip run (default) 001 = full power-down 010 = standby 011 = reset X X Duty cycle stabilizer 1 = on (default) 0 = off 0x00 0x01 0D test_io User test mode 00 = off (default) 01 = on, single alternate 10 = on, single once 11 = on, alternate once Reset PN long gen 1 = on 0 = off (default) Reset PN short gen 1 = on 0 = off (default) Output test mode--see Table 9 in the Digital Outputs and Timing section 0000 = off (default) 0001 = midscale short 0010 = +FS short 0011 = -FS short 0100 = checker board output 0101 = PN 23 sequence 0110 = PN 9 0111 = one/zero word toggle 1000 = user input 1001 = one/zero bit toggle 1010 = 1x sync 1011 = one bit high 1100 = mixed bit frequency (format determined by output_mode) 0x00 When set, the test data is placed on the output pins in place of normal data. Rev. 0 | Page 30 of 52 AD9252 Addr. (Hex) 14 Parameter Name output_mode Bit 7 (MSB) X Bit 6 0 = LVDS ANSI (default) 1 = LVDS low power, (IEEE 1596.3 similar) X Bit 5 X Bit 4 X Bit 3 X Bit 2 Output invert 1 = on 0 = off (default) Bit 0 (LSB) Bit 1 00 = offset binary (default) 01 = twos complement Default Value (Hex) 0x00 Default Notes/ Comments Configures the outputs and the format of the data. 15 output_adjust X Output driver termination 00 = none (default) 01 = 200 10 = 100 11 = 100 X X X DCO and FCO 2x drive strength 1 = on 0 = off (default) 0x00 16 output_phase X X X X 19 1A 1B 1C 21 user_patt1_lsb user_patt1_msb user_patt2_lsb user_patt2_msb serial_control B7 B15 B7 B15 LSB first 1 = on 0 = off (default) B6 B14 B6 B14 X B5 B13 B5 B13 X B4 B12 B4 B12 X 0011 = output clock phase adjust (0000 through 1010) (Default: 180 relative to DATA edge) 0000 = 0 relative to DATA edge 0001 = 60 relative to DATA edge 0010 = 120 relative to DATA edge 0011 = 180 relative to DATA edge 0100 = 240 relative to DATA edge 0101 = 300 relative to DATA edge 0110 = 360 relative to DATA edge 0111 = 420 relative to DATA edge 1000 = 480 relative to DATA edge 1001 = 540 relative to DATA edge 1010 = 600 relative to DATA edge 1011 to 1111 = 660 relative to DATA edge B3 B2 B1 B0 B11 B3 B11 <10 MSPS, low encode rate mode 1 = on 0 = off (default) X B10 B2 B10 B9 B1 B9 B8 B0 B8 0x03 Determines LVDS or other output properties. Primarily functions to set the LVDS span and common-mode levels in place of an external resistor. On devices that utilize global clock divide, determines which phase of the divider output is used to supply the output clock. Internal latching is unaffected. 0x00 0x00 0x00 0x00 0x00 000 = 14 bits (default, normal bit stream) 001 = 8 bits 010 = 10 bits 011 = 12 bits 100 = 14 bits User-defined pattern, 1 LSB. User-defined pattern, 1 MSB. User-defined pattern, 2 LSB. User-defined pattern, 2 MSB. Serial stream control. Default causes MSB first and the native bit stream (global). 22 serial_ch_stat X X X X X Channel output reset 1 = on 0 = off (default) Channel powerdown 1 = on 0 = off (default) 0x00 Used to power down individual sections of a converter (local). Rev. 0 | Page 31 of 52 AD9252 Power and Ground Recommendations When connecting power to the AD9252, it is recommended that two separate 1.8 V supplies be used: one for analog (AVDD) and one for digital (DRVDD). If only one supply is available, it should be routed to the AVDD first and then tapped off and isolated with a ferrite bead or a filter choke preceded by decoupling capacitors for the DRVDD. The user can employ several different decoupling capacitors to cover both high and low frequencies. These should be located close to the point of entry at the PC board level and close to the parts with minimal trace length. A single PC board ground plane should be sufficient when using the AD9252. With proper decoupling and smart partitioning of the PC board's analog, digital, and clock sections, optimum performance is easily achieved. Exposed Paddle Thermal Heat Slug Recommendations It is required that the exposed paddle on the underside of the ADC is connected to analog ground (AGND) to achieve the best electrical and thermal performance of the AD9252. An exposed continuous copper plane on the PCB should mate to the AD9252 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be solder filled or plugged. To maximize the coverage and adhesion between the ADC and PCB, partition the continuous copper plane by overlaying a silkscreen on the PCB into several uniform sections. This provides several tie points between the two during the reflow process. Using one continuous plane with no partitions only guarantees one tie point between the ADC and PCB. See Figure 59 for a PCB layout example. For detailed information on packaging and the PCB layout of chip scale packages, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP), at www.analog.com. SILKSCREEN PARTITION PIN 1 INDICATOR Figure 59. Typical PCB Layout Rev. 0 | Page 32 of 52 06296-034 AD9252 EVALUATION BOARD The AD9252 evaluation board provides all of the support circuitry required to operate the ADC in its various modes and configurations. The converter can be driven differentially through a transformer (default) or through the AD8334 driver. The ADC can also be driven in a single-ended fashion. Separate power pins are provided to isolate the DUT from the AD8334 drive circuitry. Each input configuration can be selected by proper connection of various jumpers (see Figure 62 to Figure 66). Figure 60 shows the typical bench characterization setup used to evaluate the ac performance of the AD9252. It is critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the optimum performance of the converter. Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is also necessary to achieve the specified noise performance. See Figure 62 to Figure 72 for the complete schematics and layout diagrams that demonstrate the routing and grounding techniques that should be applied at the system level. capability for AVDD_DUT and DRVDD_DUT; however, it is recommended that separate supplies be used for both analog and digital. To operate the evaluation board using the VGA option, a separate 5.0 V analog supply is needed. The 5.0 V supply, or AVDD_5 V, should have a 1 A current capability. To operate the evaluation board using the SPI and alternate clock options, a separate 3.3 V analog supply is needed in addition to the other supplies. The 3.3 V supply, or AVDD_3.3 V, should have a 1 A current capability as well. INPUT SIGNALS When connecting the clock and analog source, use clean signal generators with low phase noise, such as Rohde & Schwarz SMHU or HP8644 signal generators or the equivalent. Use a 1 m, shielded, RG-58, 50 coaxial cable for making connections to the evaluation board. Enter the desired frequency and amplitude from the ADC specifications tables. Typically, most Analog Devices evaluation boards can accept ~2.8 V p-p or 13 dBm sine wave input for the clock. When connecting the analog input source, it is recommended to use a multipole, narrow-band, band-pass filter with 50 terminations. Analog Devices uses TTE, Allen Avionics, and K&L types of band-pass filters. The filter should be connected directly to the evaluation board if possible. POWER SUPPLIES This evaluation board comes with a wall-mountable switching power supply that provides a 6 V, 2 A maximum output. Simply connect the supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz. The other end is a 2.1 mm inner diameter jack that connects to the PCB at P701. Once on the PC board, the 6 V supply is fused and conditioned before connecting to three low dropout linear regulators that supply the proper bias to each of the various sections on the board. When operating the evaluation board in a nondefault condition, L701 to L704 can be removed to disconnect the switching power supply. This enables the user to bias each section of the board individually. Use P702 to connect a different supply for each section. At least one 1.8 V supply is needed with a 1 A current WALL OUTLET 100V AC TO 240V AC 47Hz TO 63Hz 6V DC 2A MAX SWITCHING POWER SUPPLY - OUTPUT SIGNALS The default setup uses the HSC-ADC-FPGA high speed deserialization board to deserialize the digital output data and convert it to parallel CMOS. These two channels interface directly with the Analog Devices standard dual-channel FIFO data capture board (HSC-ADC-EVALB-DC). Two of the eight channels can then be evaluated at the same time. For more information on channel settings on these boards and their optional settings, visit www.analog.com/FIFO. 5.0V + - 1.8V + 1.8V - + - 3.3V + - 3.3V + - 1.5V + - 3.3V + 1.5V_FPGA GND GND GND GND GND GND AVDD_5V DRVDD_DUT AVDD_3.3V AVDD_DUT 3.3V_D GND VCC ROHDE & SCHWARZ, SMHU, 2V p-p SIGNAL SYNTHESIZER ROHDE & SCHWARZ, SMHU, 2V p-p SIGNAL SYNTHESIZER BAND-PASS FILTER XFMR INPUT AD9252 EVALUATION BOARD CLK SPI SPI SPI Figure 60. Evaluation Board Connection Rev. 0 | Page 33 of 52 06296-035 CHA TO CHH 14-BIT SERIAL LVDS HSC-ADC-FPGA HIGH SPEED DESERIALIZATION BOARD 2-CH 14-BIT PARALLEL CMOS SPI HSC-ADC-EVALB-DC FIFO DATA CAPTURE BOARD USB CONNECTION PC RUNNING ADC ANALYZER AND SPI USER SOFTWARE AD9252 DEFAULT OPERATION AND JUMPER SELECTION SETTINGS The following is a list of the default and optional settings or modes allowed on the AD9252 Rev. A evaluation board. * POWER: Connect the switching power supply that is supplied in the evaluation kit between a rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz and P701. AIN: The evaluation board is set up for a transformercoupled analog input with optimum 50 impedance matching out to 150 MHz (see Figure 61). For more bandwidth response, the differential capacitor across the analog inputs can be changed or removed. The common mode of the analog inputs is developed from the center tap of the transformer or AVDD_DUT/2. 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 0 50 100 150 200 250 300 350 400 450 500 06296-036 50 terminated and ac-coupled to handle single-ended sine wave types of inputs. The transformer converts the single-ended input to a differential signal that is clipped before entering the ADC clock inputs. A differential LVPECL clock can also be used to clock the ADC input using the AD9515 (U401). Simply populate R406 and R407 with 0 resistors and remove R215 and R216 to disconnect the default clock path inputs. In addition, populate C205 and C206 with a 0.1 F capacitor and remove C409 and C410 to disconnect the default clock path outputs. The AD9515 has many pin-strappable options that are set to a default working condition. Consult the AD9515 data sheet for more information about these and other options. If using an oscillator, two oscillator footprint options are also available (OSC401) to check the ADC performance. J401 gives the user flexibility in using the enable pin, which is common on most oscillators. * * PDWN: To enable the power-down feature, simply short J301 to the on position (AVDD) on the PDWN pin. SCLK/DTP: To enable a digital test pattern on the digital outputs of the ADC, use J304. If J304 is tied to AVDD during device power-up, Test Pattern 10 0000 0000 0000 will be enabled. See the SCLK/DTP Pin section for details. SDIO/ODM: To enable the low power, reduced signal option similar to the IEEE 1595.3 reduced range link LVDS output standard, use J303. If J303 is tied to AVDD during device power-up, it enables the LVDS outputs in a low power, reduced signal option from the default ANSI standard. This option changes the signal swing from 350 mV p-p to 200 mV p-p, which reduces the power of the DRVDD supply. See the SDIO/ODM Pin section for more details. CSB: To enable the SPI information on the SDIO and SCLK pins that is to be processed, simply tie J302 low in the always enable mode. To ignore the SDIO and SCLK information, tie J302 to AVDD. Non-SPI Mode: For users who wish to operate the DUT without using SPI, simply remove Jumpers J302, J303, and J304. This disconnects the CSB, SCLK/DTP, and SDIO/OMD pins from the control bus, allowing the DUT to operate in its simplest mode. Each of these pins has internal termination and will float to its respective level. D+, D-: If an alternative data capture method to the setup described in Figure 62 is used, optional receiver terminations, R318, R320 to R328, can be installed next to the high speed backplane connector. * -3dB CUTOFF = 186MHz AMPLITUDE (dBFS) * -14 FREQUENCY (MHz) Figure 61. Evaluation Board Full Power Bandwidth * VREF: VREF is set to 1.0 V by tying the SENSE pin to ground, R317. This causes the ADC to operate in 2.0 V p-p full-scale range. A separate external reference option using the ADR510 or ADR520 is also included on the evaluation board. Simply populate R312 and R313 and remove C307. Proper use of the VREF options is noted in the Voltage Reference section. RBIAS: RBIAS has a default setting of 10 k (R301) to ground and is used to set the ADC core bias current. To further lower the core power (excluding the LVDS driver supply), simply change the resistor setting. However, performance of the ADC will degrade depending on the resistor chosen. See RBIAS section for more information. CLOCK: The default clock input circuitry is derived from a simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T401) that adds a very low amount of jitter to the clock path. The clock input is * * * * * Rev. 0 | Page 34 of 52 AD9252 ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION The following is a brief description of the alternative analog input drive configuration using the AD8334 dual VGA. If this particular drive option is in use, some components may need to be populated, in which case all the necessary components are listed in Table 16. For more details on the AD8334 dual VGA, including how it works and its optional pin settings, consult the AD8334 data sheet. To configure the analog input to drive the VGA instead of the default transformer option, the following components need to be removed and/or changed. * Remove R102, R115, R128, R141, R202, R218, R234, R252, T101, T102, T103, T104, T201, T202, T203, and T204 in the default analog input path. * * Populate R101, R114, R127, R140, R201, R217, R233, and R251 with 0 resistors in the analog input path. Populate R106, R107, R119, R120, R132, R133, R144, R145, R206, R207, R223, R224, R239, R240, R257, and R258 with 10 k resistors to provide an input common-mode level to the analog input. Populate R105, R113, R118, R124, R131, R137, R151, and R160, R205, R213, R221, R222, R239, R240, R255, and R256 with 0 resistors in the analog input path. * Currently, L505 to L520 and L605 to L620 are populated with 0 resistors to allow signal connection. This area allows the user to design a filter if additional requirements are necessary. Rev. 0 | Page 35 of 52 AD9252 AVDD_DUT P106 DNP R105 0-DNP CH_A 1 VIN_A 1 CM3 3 FB107 10 C116 0.1F CM3 E103 AVDD_DUT AVDD_DUT R112 1k C107 0.1F R138 1k R139 1k C121 0.1F 1 CH_C R137 0-DNP R128 64.9 R129 0 4 2 5 CM3 R133 DNP 6 R132 DNP CM1 R161 499 R110 33 C103 DNP Ain VIN_A C105 DNP R156 DNP C104 2.2pF R109 1k R107 DNP FB103 10 R106 DNP Channel C P105 R127 0-DNP CM1 3 CH_A CM1 1 C106 DNP R111 1k 0-DNP R113 4 2 5 T101 6 T103 FB102 10 R108 33 R130 0 C115 0.1F CH_C R152 DNP Ain R131 0-DNP FB108 10 R134 33 VGA Input Connection INH3 AVDD_DUT DNP P102 VGA Input Connection INH1 Ain R104 0 C101 0.1F R154 DNP Channel A P101 R101 0-DNP VIN_C R163 499 C117 DNP C118 2.2pF FB109 10 Ain C102 0.1F R102 64.9 E101 FB101 10 R135 1k VIN_C R136 33 C119 DNP R103 0 R158 DNP C120 DNP AVDD_DUT AVDD_DUT VGA Input Connection AVDD_DUT INH4 R153 DNP FB105 10 R121 33 VIN_B CM2 R120 DNP C110 DNP VIN_B R142 0 FB106 10 C112 DNP R157 DNP R122 33 C111 2.2pF R141 64.9 R123 1k R119 DNP R162 499 Ain DNP P108 Ain Channel D P107 R140 0-DNP VGA Input Connection AVDD_DUT INH2 Channel B CH_B 1 T102 6 5 4 R124 0-DNP CM2 3 CH_B CM2 1 C113 DNP AVDD_DUT C114 0.1F R125 1K R126 1k 2 P103 R114 0-DNP R118 0-DNP R151 0-DNP FB110 10 C122 0.1F CH_D 1 CM4 2 3 R143 0 C123 0.1F E104 AVDD_DUT 1 C127 DNP T104 6 5 4 R160 CH_D CM4 0-DNP CM4 R145 DNP FB112 10 R144 DNP FB111 10 R146 33 R155 DNP FB104 10 DNP: DO NOT POPULATE. 06296-072 Figure 62. Evaluation Board Schematic, DUT Analog Inputs E102 R149 1k R150 1k C128 0.1F Rev. 0 | Page 36 of 52 Ain C108 0.1F VIN_D R164 499 C124 DNP C125 2.2pF R148 1k VIN_D R147 33 R115 64.9 DNP P104 Ain C109 0.1F R116 0 R117 0 C126 DNP R159 DNP AVDD_DUT AVDD_DUT AVDD_DUT AVDD_DUT DNP P206 Ain R236 0 1 CM7 3 R234 64.9k R235 0 E203 AVDD_DUT FB207 10 C216 0.1F 1 CH_G CM7 R238 0-DNP 2 T203 6 5 4 CM7 R240 DNP FB209 10 R239 DNP R241 499 Channel G R233 0-DNP C215 0.1F CH_G R237 0-DNP FB208 10 R242 33 VIN_G C217 DNP C218 2.2pF R246 1k VIN_G R245 33 C219 DNP VGA Input Connection R205 0-DNP CH_E 1 6 VIN_E CM5 R208 499 R210 33 C203 DNP Ain VIN_E C205 DNP R215 DNP C204 2.2pF P205 R214 1k R207 DNP FB203 10 R206 DNP 5 4 R213 0-DNP CM5 3 CH_E CM5 1 C206 DNP AVDD_DUT C207 0.1F R211 1k R212 1k 2 T201 FB202 10 R209 33 R216 DNP INH7 C201 0.1F DNP P202 VGA Input Connection INH5 Ain R248 DNP Channel E C202 0.1F R204 0 P201 R201 0-DNP Ain FB201 10 R202 64.9 E201 R203 0 R247 DNP AVDD_DUT C220 DNP R249 1k R250 1k C221 0.1F AVDD_DUT VGA Input Connection INH8 Channel H DNP P207 VIN_F Ain R252 64.9 VIN_F DNP P208 Ain CM6 R225 499 R227 33 C210 DNP FB206 10 C212 DNP R229 DNP C211 2.2pF R228 1k R223 DNP R251 0-DNP AVDD_DUT VGA Input Connection AVDD_DUT INH6 Channel F R221 0-DNP CH_F 1 CM6 3 CH_F 0-DNP CM6 1 C213 DNP R231 1k AVDD_DUT R232 1k C214 0.1F R222 R224 DNP 4 2 5 T202 6 C208 0.1F FB205 10 R226 33 P203 R217 0-DNP R230 DNP R255 0-DNP FB210 10 C222 0.1F CH_H 1 CM8 2 3 R254 0 R253 0 CH_H C223 0.1F CM8 E204 AVDD_DUT 1 C227 DNP R256 0-DNP T204 6 5 4 CM8 R258 DNP FB212 10 R257 DNP R259 499 FB211 10 R264 DNP R260 33 VIN_H C224 DNP C225 2.2pF R262 1k VIN_H R261 33 C226 DNP Figure 63. Evaluation Board Schematic, DUT Analog Inputs (Continued) C209 0.1F E202 AVDD_DUT R265 1k R266 1k C228 0.1F DNP: DO NOT POPULATE. 06296-073 Rev. 0 | Page 37 of 52 Ain FB204 10 R218 64.9 DNP P204 Ain R220 0 R219 0 R263 DNP AVDD_DUT AD9252 C301 0.1F Reference Decoupling AD9252 C303 4.7F C304 0.1F C302 0.1F R301 10k AVDD_DUT VIN_E AVDD_DUT VIN_E VIN_F VIN_F Digital Outputs P301 GNDCD10 60 VIN_D VIN_C VIN_C DCO FCO CHA 48 AVDD_DUT VIN_D VSENSE_DUT DCO 40 GNDCD9 50 59 VREF_DUT C10 D10 D9 GNDCD8 49 R318 DNP R320 DNP R321 FCO 39 58 C9 C8 GNDCD7 64 60 59 58 57 56 55 54 51 50 49 CHA 38 57 53 52 0 D8 REFT VREF REFB AVDD AVDD VIN+E VIN-D VIN-C VIN+D VIN+C RBIAS 48 AVDD_DUT 56 37 GNDCD6 63 AVDD_DUT CHB C7 C6 C5 C4 34 53 33 52 62 61 SLUG AVDD VIN-F VIN+F VIN-E SENSE AVDD_DUT VIN+B VIN_B 55 1 AVDD 47 36 AVDD CHC CHD 35 54 GNDCD5 D7 D6 D5 47 CHB CHC 46 DNP R322 DNP R323 VIN_G R302 DNP VIN-B AVDD AVDD_DUT VIN_A VIN_A PDWN ENABLE 2 46 VIN_B R303 100k CHE CHF 3 CHG CHH 3 ALWAYS ENABLE SPI VIN+G R318,R320-R328 Optional Output Terminations GNDCD4 45 VIN_G 45 44 43 2 42 AVDD_DUT CSB_DUT 1 J302 2 41 40 39 1 3 1k 2 J304 3 2 38 37 AVDD_DUT GND DRVDD_DUT R307 10k R305 100k R306 100k CHA CHA 36 35 34 33 SCLK_DTP 1 R319 J303 SDIO_ODM ODM Enable 3 R304 DNP VIN-G CHD CHE GNDCD3 DNP R324 D4 44 AVDD_DUT VIN-A VIN+A AVDD 1 J301 4 AVDD DNP R325 C3 32 51 31 30 10 29 9 28 8 27 GNDCD2 VIN_H 5 VIN-H D3 C2 C1 A10 A9 A8 7 GNDCD1 43 CHF D2 GNDAB10 42 VIN_H 6 DNP R326 CHG D1 B10 GNDAB9 41 VIN+H AVDD_DUT 7 DNP R327 CHH 20 AVDD AVDD_DUT PDWN CSB 8 AVDD AD9252BCPZ-50 DNP R328 DNP B9 GNDAB8 CLK 9 CLK- CLK SDIO/ODM SCLK/DTP AVDD DRGND DRVDD D+A D-A D+D D+C D-D D-C D+B D-B 10 CLK+ U301 19 AVDD_DUT 11 B8 GNDAB7 AVDD 18 AVDD_DUT 12 AVDD DTP Enable A7 26 6 B7 GNDAB6 17 GND 13 DRGND A6 SCLK_CHB SDI_CHB CSB3_CHB CSB4_CHB SDO_CHB 25 5 24 4 23 3 22 2 21 1 B6 GNDAB5 16 DNP: DO NOT POPULATE. Remove C214 when using external Vref 06296-074 Figure 64. Evaluation Board Schematic, DUT, VREF, and Digital Output Interface Rev. 0 | Page 38 of 52 DCO- DCO+ FCO- FCO+ D+E D-E 21 23 24 25 26 27 31 29 22 28 30 32 CHB CHB FCO FCO CHD CHD CHC CHC DCO DCO CHE CHE DRVDD_DUT 14 DRVDD A5 A4 A3 A2 A1 B5 GNDAB4 15 SCLK_CHA B4 GNDAB3 14 CHH 15 D-H SDI_CHA B3 GNDAB2 13 CHH 16 D+H CSB1_CHA B2 GNDAB1 12 D+G AVDD_DUT OPTIONAL EXT REF U302 ADR510ARTZ TRIM/NC 1.0V VOUT AVDD_DUT R312 DNP C305 0.1F C306 0.1F R310 10k CW C307 1F R313 DNP GND R309 4.99k D-G D+F D-F CSB2_CHA B1 11 17 19 18 20 SDO_CHA CHF CHF CHG CHG NC Reference Circuitry R311 DNP VREF_DUT Vref Select R314 DNP VREF = 0.5V R315 DNP VSENSE_DUT VREF = External R31 DNP R317 0 R308 470k VREF = 0.5V(1 + R219/R220) VREF = 1V AVDD_3.3V C401 0.1F AVDD_3.3V 3 ENABLE OSC401 2 J401 DISABLE OSC401 1 OPT_CLK U401 CLK R424 OUT0 OUT0B S0 R426 AVDD_3.3V DNP S1 R428 AVDD_3.3V R423 100 DNP LVDS OUTPUT C407 0.1F DNP S2 R430 AVDD_3.3V S10 R417 0 CLK C408 0.1F DNP S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 DNP R446 DNP S3 R432 AVDD_3.3V DNP CLIP SINE OUT (DEFAULT) S4 R434 AVDD_3.3V CLK S5 DNP 0 0 0 0 19 18 R420 240 R421 240 0 22 CLK 23 R422 100 LVPECL OUTPUT AVDD_3.3V DNP R427 0 DNP 0.1F C406 R408 DNP DNP 0.1F C405 R409 DNP R410 10k R414 4.12k AVDD_3.3V R401 10k OPTIONAL CLOCK DRIVE CIRCUIT AVDD_3.3V Optional Clock Oscillator OSC401 14 VCC OE 1 32 1 31 33 12 VCC OE 3 R425 0 VS GND_PAD GND RSET 10 R411 49.9 DNP 3 CLKB SIGNAL=AVDD_3.3V;4,17,20,21,24,26,29,30 SYNCB SIGNAL=DNC;27,28 OUT1B OUT1 OUT GND 5 R402 10k CLK R406 0 DNP 2 AD9515 Pin-strap settings R436 0 AVDD_3.3V 0 S6 R429 0 R438 AVDD_3.3V DNP R431 0 S7 R440 AVDD_3.3V DNP S8 R433 0 R442 AVDD_3.3V DNP S9 R435 0 R444 AVDD_3.3V DNP S10 0 R445 0 0 R443 0 0 R441 0 0 R439 0 R437 DNP 0 8 OPT_CLK 5 R413 10k OUT GND 7 AD9515BCPZ Encode OPT_CLK R407 0 R412 DNP DNP CRYSTAL_3 Input R403 0 DNP VREF P401 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 7 8 9 6 Enc 10 11 12 13 14 15 16 25 C402 0.1F 1 E401 R404 49.9 Clock Circuit OPT_CLK R415 T401 3 CR401 HSMS-2812-TR1G 2 5 4 DNP P402 3 Enc 0 R416 0.1F C409 2 06296-075 Figure 65. Evaluation Board Schematic, Clock Circuitry 1 Rev. 0 | Page 39 of 52 0 R418 0 1 6 C411 0.1F C410 0.1F C 41 2 0.1F R405 0 C403 0.1F AVDD_3.3V C413 0.1F C 4 14 0.1F C 415 0.1F C416 0.1F C417 0.1F C 4 18 0.1F DNP: DO NOT POPULATE. AD9252 AD9252 EXT VG DNP 10k R506 Rclamp Pin HILO Pin=LO=+/- 50mV HILO Pin=H=+/- 75mV R505 10k C510 10F C543 DNP C547 DNP L508 0 L511 0 L512 0 L515 0 AVDD_5V L507 0 C509 0.1F C551 DNP L516 0 L519 0 R517 DNP R529 DNP R522 DNP AVDD_5V CH_D CH_B CH_D CH_C CH_C CH_B CH_A 1 C507 1000pF C508 0.1F JP501 Power Down Enable (0-1V=Disable Power) Populate L505-L520 with 0 resistors or design your own filter. CH_A 2 GND VG12 C502 0.018F R503 274 C505 0.1F C542 DNP C546 DNP L506 0 R521 DNP L509 0 L510 0 L505 0 R516 DNP C512 10F C550 DNP L513 0 R528 DNP L514 0 0.1F C501 R504 10k AVDD_5V C506 VG12 L501 120nH 0.1F C503 22pF C504 0.1F U501 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 C540 0.1F R515 374 R514 187 R518 187 C541 0.1F C511 0.1F VIN1 VIP1 EN34 EN12 LON1 VPS1 LOP1 LMD1 VCM1 VCM2 INH1 COM1 CLMP12 COM2 GAIN12 COM1X C544 0.1F C545 0.1F C548 0.1F R527 374 R520 374 R519 187 R525 187 AVDD_5V 46 45 44 43 42 R523 10k 41 40 39 38 37 VOL3 VPS34 VOL4 VOH4 COM34 CLMP34 GAIN34 COM4X COM4 VCM3 VCM4 LON4 VPS4 LOP4 LMD4 36 35 34 33 AVDD_5V AVDD_5V R526 187 C549 0.1F R513 187 1 INH2 LMD2 VOH1 VOL1 VPS12 VOL2 VOH2 COM12 COM2X LON2 LOP2 VIP2 VIN2 VPS2 MODE NC COM34 VOH3 VPS3 VIN3 VIP3 LOP3 LON3 COM3X LMD3 INH3 COM3 47 COM12 2 C537 0.1F 3 4 C518 5 6 7 AVDD_5V AVDD_5V 10 11 0.1F C522 C523 0.1F 13 14 15 C524 0.1F 16 12 9 8 C538 0.1F 0.1F R507 274 C515 0.018F 48 C514 22pF R524 10k R534 DNP VG12 R501 10k CW External Variable Gain Drive C555 DNP L520 0 R502 39k Variable Gain Circuit (0-1.0V DC) C554 DNP L517 0 L518 0 R533 DNP INH3 AVDD_5V INH4 C552 0.1F R532 374 R530 187 C553 0.1F 0.1F C513 R531 187 L502 120nH AD8334ACPZ-REEL 06296-076 Figure 66. Evaluation Board Schematic, Optional DUT Analog Input Drive MODE Pin Positive Gain Slope = 0-1.0V Negitive Gain Slope = 2.25-5.0V Rev. 0 | Page 40 of 52 R508 274 C521 0.018F HILO INH4 VIN4 VIP4 NC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 C520 22pF C533 10F C529 VG34 AVDD_5V C528 0.1F 0.1F C534 0.1F L504 120nH C535 10F INH1 C527 0.018F 0.1F C525 AVDD_5V C530 0.1F R509 274 R512 10k C526 22pF C536 0.1F Rclamp Pin C531 1000pF C532 0.1F HILO Pin=LO=+/- 50mV HILO Pin=H=+/- 75mV DNP 10k R510 R511 10k L503 120nH INH2 0.1F C519 EXT VG 1 JP502 2 GND VG34 VG34 R535 10k CW DNP: DO NOT POPULATE. External Variable Gain Drive R536 39k Variable Gain Circuit (0-1.0V DC) AVDD_5V MODE Pin Power Down Enable (0-1V=Disable Power) C607 1000pF C608 0.1F Rclamp Pin HILO Pin=LO=+/- 50mV HILO Pin=H=+/- 75mV R617 DNP R629 DNP R622 DNP DNP 10k R606 AVDD_5V CH_H CH_F CH_F CH_H CH_G CH_G Positive Gain Slope = 0-1.0V Negative Gain Slope = 2.25-5.0V Populate L605-L620 with 0 resistors or design your own filter. EXT VG JP601 1 2 CH_E CH_E GND VG56 R605 10k C610 10F C643 DNP C647 DNP L608 0 L611 0 L612 0 C651 DNP L615 0 R636 DNP VG56 R601 10k CW External Variable Gain Drive AVDD_5V L607 0 C655 DNP L616 0 L619 0 L620 0 C609 0.1F R602 39k C602 0.018F R603 274 C605 0.1F C642 DNP C646 DNP L606 0 L609 0 L610 0 R621 DNP L605 0 R616 DNP Variable Gain Circuit (0-1.0V DC) AVDD_5V C606 C650 DNP L613 0 R628 DNP L614 0 L617 0 C654 DNP L618 0 R633 DNP 0.1F C601 INH7 INH2 LMD2 VOH1 VOL1 VPS12 VOL2 VOH2 COM12 42 41 40 39 VOH3 VOL3 VPS34 VOL4 VOH4 COM34 38 37 36 35 34 33 43 44 45 46 COM2X LON2 LOP2 VIP2 VIN2 VPS2 MODE NC COM34 VPS3 VIN3 VIP3 LOP3 LON3 COM3X LMD3 INH3 47 COM12 2 AVDD_5V R604 VG56 L601 120nH 0.1F INH8 C603 22pF C612 10F 10k C604 0.1F U601 64 C640 0.1F 63 C611 0.1F VIN1 VIP1 EN34 EN12 LON1 LOP1 VPS1 VCM1 VCM2 LMD1 INH1 COM1 COM1X GAIN12 CLMP12 62 61 60 59 58 57 56 55 54 53 52 51 50 49 C641 0.1F C644 0.1F C645 0.1F R620 374 C648 0.1F C649 0.1F R627 374 C652 0.1F R632 374 C653 0.1F COM2 0.1F C613 R613 187 1 48 R615 374 R614 187 R618 187 R619 187 R625 187 AVDD_5V R626 187 R630 187 R631 187 L602 120nH C615 0.018F C616 0.1F 3 4 C618 C617 0.1F 0.1F 6 7 AVDD_5V AVDD_5V 10 11 0.1F C622 C623 0.1F 13 14 15 C624 0.1F 16 12 9 8 5 C614 22pF R607 274 AVDD_5V R624 10k 06296-077 Figure 67. Evaluation Board Schematic, Optional DUT Analog Input Drive (Continued) AD8334ACPZ-REEL Rev. 0 | Page 41 of 52 R608 274 C621 0.018F CLMP34 GAIN34 COM4X COM4 COM3 VCM3 VCM4 LON4 LOP4 VPS4 LMD4 HILO VIN4 VIP4 INH4 NC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 C620 22pF C629 R623 10k AVDD_5V L603 120nH INH6 0.1F C619 EXT VG 1 JP602 2 C633 10F VG78 AVDD_5V C628 0.1F 0.1F GND VG78 L604 120nH INH5 C634 0.1F VG78 R634 10k AVDD_5V C630 0.1F CW DNP: DO NOT POPULATE. External Variable Gain Drive C627 0.018F 0.1F C625 C626 22pF R609 274 C635 10F R612 10k R635 39k C636 0.1F Variable Gain Circuit (0-1.0V DC) C631 1000pF C632 0.1F Rclamp Pin HILO Pin=LO=+/- 50mV HILO Pin=H=+/- 75mV DNP 10k R610 R611 10k AVDD_5V AD9252 AD9252 SPI CIRCUITRY FROM FIFO Power Supply Input 6V, 2A max REMOVE WHEN USING OR PROGRAMMING PIC (U402) F701 FER701 1 NANOSMDC110F-2 1 C704 D701 10F 2 3 0 0 0 0 7.5V POWER CON005 2.5MM JACK S2A-TP AVDD_3.3V 4 3 2 SK33-TP D702 PWR_IN SDI_CHA CSB1_CHA SDO_CHA SCLK_CHA +5V = PROGRAMMING = AVDD_5V +3.3V = NORMAL OPERATION = AVDD_3.3V AVDD_3.3V P701 R708 R709 R707 R706 AVDD_5V 1 J701 3 CR702 GREEN 2 C701 0.1F R710 1k R703 0-DNP 0-DNP 0-DNP Optional Power Input P702 DNP SDIO_ODM P1 P2 P3 NC7W207P6X_NL 1 A1 P5 AVDD_DUT P7 P8 U702 C702 0.1F 8 7 P6 6 DUT_DRVDD C705 10F E701 1 R711 10k 3 A2 Y2 4 GND VCC 2 5 Y1 6 R713 1k 5 DUT_AVDD L701 10H R712 1k AVDD_DUT P4 4 3 5V_AVDD 2 1 3.3V_AVDD L703 10H R705 R704 U701 1 VDD VSS 8 S701 R701 4.7k 2 GP5 GP0 7 R716 261 3 1 3 GP4 GP1 6 4 2 4 MCLR/GP3 GP2 5 PIC12F629-I/SNG RESET/ REPROGRAM R702 261 AVDD_3.3V C709 10F C710 0.1F +3.3V CR701 PIC PROGRAMMING HEADER OPTIONAL GREEN NC7WZ16P6X_NL 1 A1 Y1 6 SCLK_DTP AVDD_DUT CSB_DUT C723 0.1F AVDD_5V C724 0.1F C725 0.1F C726 0.1F C727 0.1F VCC 5 Y2 4 2 GND 3 A2 Decoupling Capacitors AVDD_5V C706 0.1F +5.0V MCLR/GP3 PICVCC GP0 GP1 9 7 ISP 5 3 1 J702 L702 10H AVDD_DUT C707 10F +1.8V 10 8 6 4 2 06296-078 Figure 68. Evaluation Board Schematic, Power Supply Inputs and SPI Interface Circuitry L704 10H C703 0.1F U703 R714 10k AVDD_DUT C730 0.1F C731 0.1F C732 0.1F C733 0.1F C734 0.1F C735 0.1F AVDD_5V U705 L705 10H ADP3339ZAKC-3.3-RL DUT_AVDD PWR_IN OUT 4 OUT GND C720 1F C719 1F 1 3 IN 2 L707 10H 3.3V_AVDD AVDD_DUT C745 0.1F C744 0.1F C746 0.1F C747 0.1F C748 0.1F C749 0.1F C750 0.1F C751 0.1F R715 10k C711 10F C715 1F U706 L706 10H ADP3339ZAKC-5-RL7 DUT_DRVDD PWR_IN IN GND C717 1F C721 1F 1 3 2 OUT 4 OUT L708 10H 5V_AVDD C722 1F C740 0.1F C741 0.1F AVDD_3.3V DRVDD_DUT C742 0.1F C743 0.1F Rev. 0 | Page 42 of 52 C708 0.1F GP0 GP1 PICVCC MCLR/GP3 DRVDD_DUT C712 0.1F +1.8V U707 PWR_IN 3 ADP3339ZAKC-1.8-RL IN 2 C752 0.1F C753 0.1F OUT OUT 4 GND C714 1F 1 U704 PWR_IN 3 ADP3339ZAKC-1.8-RL IN 2 OUT 4 OUT GND C716 1F 1 DNP: DO NOT POPULATE. AD9252 Figure 69. Evaluation Board Layout, Primary Side Rev. 0 | Page 43 of 52 06296-079 AD9252 Figure 70. Evaluation Board Layout, Ground Plane Rev. 0 | Page 44 of 52 06296-080 AD9252 Figure 71. Evaluation Board Layout, Power Plane Rev. 0 | Page 45 of 52 06296-081 AD9252 Figure 72. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev. 0 | Page 46 of 52 06296-082 AD9252 Table 16. Evaluation Board Bill of Materials (BOM) 1 Qty per Board 1 118 Manufacturer Part Number GRM155R71C104KA88D Item 1 2 3 8 4 8 5 6 7 1 4 8 REFDES AD9252LFCSP_REVA C101, C102, C107, C108, C109, C114, C115, C116, C121, C122, C123, C128, C201, C202, C207, C208, C209, C214, C215, C216, C221, C222, C223, C228, C301, C302, C304, C305, C306, C401, C402, C403, C409, C410, C411, C412, C413, C414, C415, C416, C417, C418, C501, C504, C505, C506, C508, C509, C511, C513, C518, C519, C522, C523, C524, C525, C528, C529, C530, C532, C534, C536, C537, C538, C601, C604, C605, C606, C608, C609, C611, C613, C616, C617, C618, C619, C622, C623, C624, C625, C628, C629, C630, C632, C634, C636, C701, C702, C703, C706, C708, C710, C712, C723, C724, C725, C726, C727, C730, C731, C732, C733, C734, C735, C740, C741, C742, C743, C744, C745, C746, C747, C748, C749, C750, C751, C752, C753 C104, C111, C118, C125, C204, C211, C218, C225 C510, C512, C533, C535, C610, C612, C633, C635 C303 C507, C531, C607, C631 C502, C515, C521, C527, C602, C615, C621, C627 Device PCB Capacitor Package PCB 402 Value PCB 0.1 F, ceramic, X5R, 10 V, 10% tol Manufacturer Murata Capacitor 402 2.2 pF, ceramic, COG, 0.25 pF tol, 50 V 10 F, 6.3 V 10% ceramic, X5R 4.7 F, ceramic, X5R, 6.3 V, 10% tol 1000 pF, ceramic, X7R, 25 V, 10% tol 0.018 F, ceramic, X7R, 16 V, 10% tol Murata GRM1555C1H2R20CZ01D Capacitor 805 Murata GRM219R60J106KE19D Capacitor Capacitor Capacitor 603 402 402 Murata Murata AVX GRM188R60J475KE19D GRM155R71H102KA01D 0402YC183KAT2A Rev. 0 | Page 47 of 52 AD9252 Item 8 Qty per Board 8 REFDES C503, C514, C520, C526, C603, C614, C620, C626 C704 C307, C714, C715, C716, C717, C719, C720, C721, C722 C540, C541, C544, C545, C548, C549, C552, C553, C640, C641, C644, C645, C648, C649, C652, C653 C705, C707, C709, C711 CR401 CR701, CR702 D702 D701 F701 FER701 FB101, FB102, FB103, FB104, FB105, FB106, FB107, FB108, FB109, FB110, FB111, FB112, FB201, FB202, FB203, FB204, FB205, FB206, FB207, FB208, FB209, FB210, FB211, FB212 JP501, JP502, JP601, JP602 J301, J302, J303, J304, J401, J701 J702 Device Capacitor Package 402 Value 22 pF, ceramic, NPO, 5% tol, 50 V 10 F, tantalum, 16 V, 20% tol 1 F, ceramic, X5R, 6.3 V, 10% tol 0.1 F, ceramic, X7R, 50 V, 10% tol Manufacturer Murata Manufacturer Part Number GRM1555C1H220JZ01D 9 10 1 9 Capacitor Capacitor 1206 603 Rohm Murata TCA1C106M8R GRM188R61C105KA93D 11 16 Capacitor 805 Murata GRM21BR71H104KA01L 12 13 14 15 16 17 18 19 4 1 2 1 1 1 1 24 Capacitor Diode LED Diode Diode Fuse Choke coil Ferrite bead 603 SOT-23 603 DO214AB DO214AA 1210 2020 603 10 F, ceramic, X5R, 6.3 V, 20% tol 30 V, 20 mA, dual Schottky Green, 4 V, 5 m candela 3 A, 30 V, SMC 5 A, 50 V, SMC 6.0 V, 2.2 A trip-current resettable fuse 10 H, 5 A, 50 V, 190 @ 100 MHz 10 , test frequency 100 MHz, 25% tol, 500 mA Murata Agilent Technologies Panasonic Micro Commercial Co. Micro Commercial Co. Tyco/Raychem Murata Murata GRM188R60J106ME47D HSMS-2812-TR1G LNJ314G8TRA SK33-TP S2A-TP NANOSMDC110F-2 DLW5BSN191SQ2L BLM18BA100SN1D 20 21 23 4 6 1 Connector Connector Connector 2-pin 3-pin 10-pin 24 8 25 8 L701, L702, L703, L704, L705, L706, L707, L708 L501, L502, L503, L504, L601, L602, L603, L604 Ferrite bead 1210 100 mil header jumper, 2-pin 100 mil header jumper, 3-pin 100 mil header, male, 2 x 5 double row straight 10 H, bead core 3.2 x 2.5 x 1.6 SMD, 2 A 120 nH, test freq 100 MHz, 5% tol, 150 mA Samtec Samtec Samtec TSW-102-07-G-S TSW-103-07-G-S TSW-105-08-G-D Murata BLM31PG500SN1L Inductor 402 Murata LQG15HNR12J02D Rev. 0 | Page 48 of 52 AD9252 Item 26 Qty per Board 32 REFDES L505, L506, L507, L508, L509, L510, L511, L512, L513, L514, L515, L516, L517, L518, L519, L520, L605, L606, L607, L608, L609, L610, L611, L612, L613, L614, L615, L616, L617, L618, L619, L620 OSC401 Device Resistor Package 805 Value 0 , 1/8 W, 5% tol Manufacturer NIC Components Corp. Manufacturer Part Number NRC04Z0TRF 27 1 Oscillator SMT 28 9 29 1 P101, P103, P105, P107, P201, P203, P205, P207, P401 P301 Connector SMA Clock oscillator, 50.00 MHz, 3.3 V, 5% duty cycle Side-mount SMA for 0.063" board thickness 1469169-1, right angle 2-pair, 25 mm, header assembly RAPC722, power supply connector 10 k, 1/16 W, 5% tol Valphey Fisher VFAC3H-L-50MHz Johnson Components Tyco 142-0701-851 Connector HEADER 6469169-1 30 31 1 21 P701 R301, R307, R401, R402, R410, R413, R504, R505, R511, R512, R523, R524, R604, R605, R611, R612, R623, R624, R711, R714, R715 R103, R117, R129, R142, R203, R219, R235, R253, R317, R405, R415, R416, R417, R418, R706, R707, R708, R709 R102, R115, R128, R141, R202, R218, R234, R252 R104, R116, R130, R143, R204, R220, R236, R254 R109, R111, R112, R123, R125, R126, R135, R138, R139, R148, R149, R150, R211, R212, R214, R228, R231, R232, R246, R249, R250, R262, R265, R266, R319, R710, R712, R713 R108, R110, R121, R122, R134, R136, R146, R147, R209, R210, R226, R227, R242, R245, R260, R261 Connector Resistor 0.1", PCMT 402 Switchcraft NIC Components Corp. RAPC722X NRC04J103TRF 32 18 Resistor 402 0 , 1/16 W, 5% tol NIC Components Corp. NRC04Z0TRF 33 8 Resistor 402 64.9 , 1/16 W, 1% tol 0 , 1/10 W, 5% tol 1 k, 1/16 W, 1% tol 34 8 Resistor 603 35 28 Resistor 402 NIC Components Corp. NIC Components Corp. NIC Components Corp. NRC04F64R9TRF NRC06Z0TRF NRC04F1001TRF 36 16 Resistor 402 33 , 1/16 W, 5% tol NIC Components Corp. NRC04J330TRF Rev. 0 | Page 49 of 52 AD9252 Item 37 Qty per Board 8 REFDES R161, R162, R163, R164, R208, R225, R241, R259 R303, R305, R306 Device Resistor Package 402 Value 499 , 1/16 W, 1% tol 100 k, 1/16 W, 1% tol 4.12 k, 1/16W, 1% tol 49.9 , 1/16 W, 0.5% tol 4.99 k, 1/16 W, 5% tol 10 k, Cermet trimmer potentiometer, 18 turn top adjust, 10%, 1/2 W 470 k, 1/16 W, 5% tol 39 k, 1/16 W, 5% tol 187 , 1/16 W, 1% tol Manufacturer NIC Components Corp. NIC Components Corp. NIC Components Corp. Susumu NIC Components Corp. COPAL ELECTRONICS NIC Components Corp. NIC Components Corp. NIC Components Corp. Manufacturer Part Number NRC04F4990TRF 38 3 Resistor 402 NRC04F1003TRF 39 1 R414 Resistor 402 NRC04F4121TRF 40 41 1 1 R404 R309 Resistor Resistor 402 402 RR0510R-49R9-D NRC04F4991TRF 42 5 R310, R501, R535, R601, R634 R308 Potentiometer 3-lead CT94EW103 43 1 Resistor 402 NRC04J474TRF 44 4 R502, R536, R602, R635 R513, R514, R518, R519, R525, R526, R530, R531, R613, R614, R618, R619, R625, R626, R630, R631 R515, R520, R527, R532, R615, R620, R627, R632 R503, R507, R508, R509, R603, R607, R608, R609 R425, R427, R429, R431, R433, R435, R436, R439, R441, R443, R445 R701 Resistor 402 NRC04J393TRF 45 16 Resistor 402 NRC04F1870TRF 46 8 Resistor 402 374 , 1/16 W, 1% tol 274 , 1/16 W, 1% tol 0 , 1/20 W, 5% tol 47 8 Resistor 402 48 11 Resistor 201 NIC Components Corp. NIC Components Corp. NIC Components Corp. NIC Components Corp. NIC Components Corp. NIC Components Corp. NIC Components Corp. NIC Components Corp. Panasonic NRC04F3740TRF NRC04F2740TRF NRC02Z0TRF 49 1 Resistor 402 4.7 k, 1/16 W, 1% tol 261 , 1/16 W, 1% tol 261 , 1/16 W, 1% tol 240 , 1/16 W, 5% tol 100 , 1/16 W, 1% tol LIGHT TOUCH, 100GE, 5 mm NRC04J472TRF 50 1 R702 Resistor 402 NRC04F2610TRF 51 1 R716 Resistor 603 NRC06F261OTRF 52 2 R420, R421 Resistor 402 NRC04J241TRF 53 2 R422, R423 Resistor 402 NRC04F1000TRF 54 1 S701 Switch SMD EVQ-PLDA15 Rev. 0 | Page 50 of 52 AD9252 Item 55 Qty per Board 9 REFDES T101, T102, T103, T104, T201, T202, T203, T204, T401 U704, U707 Device Transformer Package CD542 Value ADT1-1WT+, 1:1 impedance ratio transformer ADP33339AKC-1.8-RL, 1.5 A, 1.8 V LDO regulator AD8334ACPZ-REEL, ultralow noise precision dual VGA ADP33339AKC-5-RL7 ADP33339AKC-3.3-RL AD9252BCPZ-50, octal, 14-bit, 50 MSPS serial LVDS 1.8 V ADC ADR510ARTZ, 1.0 V, precision low noise shunt voltage reference AD9515BCPZ, 1.6 GHz clock distribution IC NC7WZ07P6X_NL, UHS dual buffer NC7WZ16P6X_NL, UHS dual buffer Flash prog mem 1kx14, RAM size 64 x 8, 20 MHz speed, PIC12F controller series Manufacturer Mini-Circuits Manufacturer Part Number ADT1-1WT+ 56 2 IC SOT-223 Analog Devices ADP3339AKCZ-1.8-RL 57 2 U501, U601 IC CP-64-3 Analog Devices AD8334ACPZ-REEL 58 59 60 1 1 1 U706 U705 U301 IC IC IC SOT-223 SOT-223 CP-64-3 Analog Devices Analog Devices Analog Devices ADP3339AKCZ-5-RL7 ADP3339AKCZ-3.3-RL AD9252BCPZ-50 61 1 U302 IC SOT-23 Analog Devices ADR510ARTZ 62 63 64 65 1 1 1 1 U401 U702 U703 U701 IC IC IC IC LFCSP CP-32-2 SC70, MAA06A SC70, MAA06A 8-SOIC Analog Devices Fairchild Fairchild Microchip AD9515BCPZ NC7WZ07P6X_NL NC7WZ16P6X_NL PIC12F629-I/SNG 1 This BOM is RoHS compliant. Rev. 0 | Page 51 of 52 AD9252 OUTLINE DIMENSIONS 9.00 BSC SQ 0.60 MAX 0.60 MAX 48 49 PIN 1 INDICATOR 0.30 0.25 0.18 64 1 PIN 1 INDICATOR TOP VIEW 8.75 BSC SQ EXPOSED PAD (BOTTOM VIEW) 7.25 7.10 SQ 6.95 0.50 0.40 0.30 33 32 17 16 1.00 0.85 0.80 12 MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC 0.20 REF 7.50 REF 0.25 MIN SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 Figure 73. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm x 9 mm Body, Very Thin Octal (CP-64-3) Dimensions shown in millimeters ORDERING GUIDE Model AD9252BCPZ-50 1 AD9252BCPZRL7-501 AD9252-50EBZ1 1 Temperature Range -40C to +85C -40C to +85C Package Description 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Tape and Reel Evaluation Board 063006-B Package Option CP-64-3 CP-64-3 Z = Pb-free part. (c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06296-0-10/06(0) Rev. 0 | Page 52 of 52 |
Price & Availability of AD9252BCPZRL7-50
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